Offset MIM Anti-Fuse Structure for Sub-Rule Interconnect Scaling
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Solution Overview
Problem
As integrated circuits scale down, challenges arise in fabricating memory-based structures due to limitations in reducing the size of fuse structures, which are necessary for effective programming with high voltages.
Innovation Solution
The formation of offset anti-fuse elements within the interconnect region using metal-insulator-metal (MIM) structures, which are intentionally offset from contacting metal lines to reduce the active fuse area, allowing for sub-design rule fuse areas and higher fuse yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If fuse structures are made smaller to enable scaling, then integration density improves, but manufacturing precision deteriorates due to lithography limitations
Solution Approach 1:
The patent transitions from planar fuse structures to three-dimensional MIM structures by adding vertical stacking of metal layers separated by an insulator. This dimensional change allows the fuse area to be reduced in the lateral plane while maintaining sufficient active area through vertical extension, thereby overcoming lithography resolution limits.
Solution Approach 2:
The MIM fuse structure embeds the insulator layer within stacked metal layers, creating a nested configuration where the insulator is positioned between two conductive plates. This nesting approach concentrates the fuse functionality within a compact vertical footprint, enabling smaller effective fuse areas that cannot be achieved through standard lithography alone.
2Use of energy by moving object
If fuse area is reduced to lower programming voltage, then power consumption decreases, but reliability deteriorates due to insufficient active fuse area
Solution Approach 1:
The patent changes the geometric parameters of the fuse structure by transitioning from a planar configuration to a vertical MIM configuration. This parameter change allows the lateral fuse area to be reduced (lowering programming voltage) while the vertical dimension compensates by providing sufficient active area between the metal plates, thereby maintaining reliability.
3Ease of manufacture
If standard lithography is used for fuse formation, then manufacturing simplicity is maintained, but area reduction below design rules cannot be achieved
Solution Approach 1:
The patent merges the fuse structure with the interconnect layers by using the existing metal layers as the MIM fuse electrodes. This integration allows the fuse structure to be formed using the same lithography and deposition processes as the interconnect, maintaining manufacturing simplicity while achieving sub-design rule fuse areas through the vertical MIM configuration.
Data Source
AI summary
Techniques are provided for forming an offset anti-fuse device within the interconnect region over a plurality of field effect transistor (FET) devices. The anti-fuse device can be implemented as a MIM structure within a given interconnect layer. The MIM structure has a first electrode, a dielectric structure on the first electrode, and a second electrode on the dielectric structure. A lower metal line of the interconnect region makes contact with the first electrode and an upper metal line of the interconnect region makes contact with the second electrode. The MIM structure is offset from the upper and/or lower metal lines to reduce the active fuse area between the first and second electrodes. The purposeful misalignment between the electrodes of the MIM structure and the contact metal lines allows for sub-design rule fuse areas to be achieved.