Offset Nanosheet CMOS Stack for Simplified Gate-All-Around Fabrication
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Solution Overview
Problem
Current nanosheet CMOS processing requires an additional patterning step to form separate nFET and pFET nanosheet stacks, which increases process complexity and limits flexibility in threshold voltage design for pFET devices.
Innovation Solution
A semiconductor structure is formed with an nFET nanosheet stack of suspended silicon channel material nanosheets offset by one nanosheet from a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets, eliminating the need for an additional patterning step by using alternating layers of silicon and silicon germanium alloy channel materials in both device regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate patterning steps are used to form nFET and pFET nanosheet stacks, then device performance is improved, but process complexity increases
Solution Approach 1:
The patent merges the formation of nFET and pFET nanosheet stacks into a single epitaxial growth process. Alternating layers of silicon and silicon-germanium are grown together in one continuous structure, and then selectively removed to form both nFET and pFET nanosheets simultaneously. This eliminates the need for separate patterning steps while maintaining device performance.
Solution Approach 2:
The patent segments the alternating epitaxial layers into different functional regions: silicon layers become nFET channels, silicon-germanium layers become pFET channels or are selectively removed as sacrificial material. This segmentation allows both device types to be formed from a single unified structure through selective etching processes.
2Ease of manufacture
If silicon is used as channel material for both nFET and pFET, then process simplicity is maintained, but pFET threshold voltage design flexibility is reduced
Solution Approach 1:
The patent applies local quality by using different semiconductor materials (silicon vs. silicon-germanium) in different spatial locations within the same epitaxial stack. The silicon-germanium composition can be locally adjusted to achieve desired pFET threshold voltages, while silicon regions maintain their properties for nFETs. This material differentiation occurs within a single continuous growth process.
Solution Approach 2:
The patent employs composite materials by combining silicon and silicon-germanium in alternating layers within the same epitaxial structure. This composite approach allows each material to contribute its optimal properties: silicon for nFET channel performance and silicon-germanium for tunable pFET threshold voltage, achieving both process simplicity and design flexibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process and enhances pFET reliability by allowing for improved threshold voltage design without the need for additional patterning, while maintaining the benefits of silicon channel material for nFETs.
Implementation Method 1
The gate spacer layer in the nFET device region is etched to provide a first gate spacer, and thereafter an nFET nanosheet stack is formed on and n-type doped silicon germanium alloy nanosheet by removing physically exposed portions of the fin structure and the n-type doped silicon germanium alloy layer not protected by the sacrificial gate structure and the first gate spacer
Implementation Method 2
forming a fin structure of alternating layers of a silicon channel material and a silicon germanium alloy channel material on a surface of an n-type doped silicon germanium alloy layer
Data Source
AI summary
A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.