Offset Non-Volatile Storage Elements Reduce Interference
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Solution Overview
Problem
In non-volatile semiconductor memory, such as flash memory, interference from adjacent charge storage regions and channels can cause shifts in the apparent charge stored in memory cells, leading to erroneous readings, particularly in multi-state devices where threshold voltage ranges are narrower, and this issue worsens as memory cells shrink due to short channel effects and increased oxide thickness variations.
Innovation Solution
The implementation of non-volatile storage elements with charge storage layers offset in two perpendicular directions from neighboring elements, vertically offset from each other, and coupled to a control line, reduces interference by creating a staggered arrangement of NAND strings on a common active layer, thereby minimizing the impact of electric field coupling from adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are shrunk to increase storage density, then storage capacity is improved, but interference from adjacent cells increases due to short channel effects and oxide thickness variations
Solution Approach 1:
The patent applies offsetting charge storage layers in the vertical dimension (depth) to reduce interference. By positioning charge storage layers at different depths for adjacent memory cells, the patent creates spatial separation in the depth direction, which reduces electric field coupling between neighboring cells while maintaining high storage density through continued miniaturization in planar dimensions.
2Quantity of substance
If charge storage layers are positioned closer together to increase density, then storage capacity is improved, but electric field coupling between adjacent cells increases causing threshold voltage shifts
Solution Approach 1:
The patent introduces depth offsetting as an additional spatial dimension for separation. Adjacent memory cells have their charge storage layers positioned at different depths within the oxide layer, creating vertical separation that reduces electric field coupling. This allows cells to be positioned closer in planar dimensions (improving density) while maintaining threshold voltage stability through depth-based isolation.
Solution Approach 2:
The patent applies different positioning characteristics to adjacent memory cells. Specifically, charge storage layers in neighboring cells are offset from each other in the depth direction, creating local variations in spatial arrangement. This local differentiation in positioning reduces interference between specific adjacent pairs while maintaining overall high density across the memory array.
3Quantity of substance
If multi-state memory is implemented to increase storage capacity, then data density is improved, but measurement precision deteriorates due to narrower threshold voltage ranges being more susceptible to interference
Solution Approach 1:
The patent uses depth offsetting to reduce electric field coupling, which directly benefits multi-state memory by minimizing threshold voltage shifts. The vertical separation of charge storage layers reduces interference that would otherwise cause apparent charge level shifts, thereby maintaining measurement precision for detecting subtle threshold voltage differences required for multi-state operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This offset arrangement significantly reduces interference between memory cells, maintaining accurate data storage and retrieval by maintaining the separation between threshold voltage ranges, even as memory cells shrink and interference effects increase, thus enhancing the reliability of multi-state flash memory devices.
Implementation Method 1
Both EEPROM and flash memory typically utilize a charge storage region that is positioned above and insulated from a channel region in a semiconductor substrate
Implementation Method 2
Shifts in the apparent charge stored in a charge storage region of a memory cell can occur because of interference from coupling of an electric field based on the charge stored in adjacent charge storage regions
Data Source
AI summary
A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.