Offset Passivation Layer for 3D Semiconductor Electromigration Mitigation
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Solution Overview
Problem
Conventional three-dimensional semiconductor integration structures face electromigration issues due to high current density on bonding pads, exacerbated by direct alignment of TSVs under pads, leading to concentrated current and potential open circuit failures.
Innovation Solution
Incorporating a passivation layer with offset openings to distribute current away from the TSV footprint on the bonding pad, reducing current concentration and mitigating electromigration by forming electrically conducting structures within these openings in contact with the pad, offset from the TSV contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are directly aligned under bonding pads to provide electrical connection, then electrical connectivity is achieved, but current density concentrates on the pad leading to electromigration
Solution Approach 1:
The patent introduces an additional spatial dimension by creating offset openings in the passivation layer that are laterally displaced from the TSV footprint. This dimensional offset redistributes the current path across multiple pad regions rather than concentrating it at a single alignment point, thereby reducing current density and mitigating electromigration while preserving electrical connectivity.
Solution Approach 2:
The patent segments the current path by creating multiple offset openings in the passivation layer instead of a single aligned opening. This segmentation distributes the current flow across multiple locations on the bonding pad, reducing the current density at any single point and thereby reducing electromigration effects while maintaining overall electrical connectivity.
2Ease of manufacture
If conventional via structures are used to connect interconnect layers, then manufacturing simplicity is maintained, but current carrying capacity and reliability are insufficient for 3D integration
Solution Approach 1:
The patent employs a nested structure where the TSV extends through the substrate and is nested within a broader interconnect architecture that includes offset openings and multiple conducting structures. This nested arrangement allows the TSV to provide high current carrying capacity through the substrate while the offset openings and conducting structures provide additional current paths and reliability, combining the benefits of simple TSV fabrication with enhanced current capacity.
3Power
If high current density is allowed in TSVs for high power applications, then power delivery is improved, but electromigration causes void formation and open circuit failure
Solution Approach 1:
The patent changes the spatial parameter of the current path by introducing offset openings that are laterally displaced from the TSV footprint. This parameter change redistributes the current density distribution across the bonding pad, allowing high power delivery through the TSV while reducing the localized current density that causes electromigration and void formation, thereby maintaining reliability.
Data Source
AI summary
A semiconductor structure which includes a plurality of stacked semiconductor chips in a three dimensional configuration. There is a first semiconductor chip in contact with a second semiconductor chip. The first semiconductor chip includes a through silicon via (TSV) extending through the first semiconductor chip; an electrically conducting pad at a surface of the first semiconductor chip, the TSV terminating in contact at a first side of the electrically conducting pad; a passivation layer covering the electrically conducting pad, the passivation layer having a plurality of openings; and a plurality of electrically conducting structures formed in the plurality of openings and in contact with a second side of the electrically conducting pad, the contact of the plurality of electrically conducting structures with the electrically conducting pad being offset with respect to the contact of the TSV with the electrically conducting pad.