Offset Power Pillars for Stacked Memory Power Distribution
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Solution Overview
Problem
Conventional stacked memory devices face challenges in power distribution due to the limited placement options for power spines, leading to increased resistance and reduced performance, as power must travel horizontally and vertically, complicating design and reducing efficiency.
Innovation Solution
Implementing offset pillars at the interface die of a memory system, which are connected to multiple power spines and vias, providing uniform power delivery and reducing resistance in the power delivery network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single power spine is used in conventional stacked memory devices, then the structure is simple, but the resistance increases and performance decreases due to limited placement options and longer power travel paths
Solution Approach 1:
The single power spine is segmented into multiple power spines (first power spine and second power spine) that are positioned at different locations. This segmentation reduces the resistance by distributing power delivery paths and eliminates the need for power to travel long horizontal and vertical distances, thereby improving power delivery performance without excessive complexity
Solution Approach 2:
The patent introduces offset pillars that extend in the vertical dimension between the first and second memory dies. This vertical offset configuration allows power spines to be positioned at different vertical levels, creating three-dimensional power distribution paths that reduce resistance and improve performance beyond what planar configurations can achieve
2Productivity
If power spines are positioned near the middle of dies, then placement is straightforward, but power must travel both vertically and horizontally increasing resistance and reducing efficiency
Solution Approach 1:
Multiple power spines are positioned at different horizontal locations (first power spine at first location, second power spine at second location) rather than relying on a single central power spine. This segmentation creates multiple shorter power paths, reducing the overall distance power must travel and improving delivery efficiency
Solution Approach 2:
Offset pillars positioned in the vertical dimension between memory dies create direct vertical power paths. This eliminates the need for power to travel horizontally to reach connection points, as power can be delivered directly through the vertical offset pillar structure, significantly reducing total travel distance
Data Source
AI summary
Methods, systems, and devices for offset pillars for a memory system are described. A memory system may include a memory device consisting of an interface die and one or more memory dies stacked on top of it. The interface die may include power pillars that are coupled with a power supply and configured to route power to each of the stacked dies. The interface die may be larger than the stacked dies (e.g., in a horizontal direction) such that the power pillars are located near the periphery of the stacked dies and are “offset” from the respective power pillars of the stacked dies.