Offset Planar Bus Assembly for SiC Switching Impedance
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Solution Overview
Problem
The increased impedance effects from inductance and capacitance in conductive buses and circuit components used with advanced semiconductor switching devices, such as silicon carbide transistors, lead to system performance degradation and oscillation issues.
Innovation Solution
A bus assembly design featuring interconnected planar bus sections with offset configurations and clearance holes, along with metal oxide varistors, to minimize impedance and enhance electrical connectivity between semiconductor device packages, including insulated gate bipolar transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional conductive buses and circuit components are used with advanced semiconductor switching devices, then the devices can operate at high voltage and switching frequency, but impedance effects (inductance and capacitance) increase and degrade system performance
Solution Approach 1:
The bus assembly is divided into multiple planar bus sections (first, second, third, and fourth planar bus sections) that are offset from each other. This segmentation allows the current path to be distributed across multiple sections, reducing the overall inductance and impedance effects while maintaining high switching frequency operation capability
Solution Approach 2:
The bus sections are arranged in offset parallel planes, transitioning from a single-plane configuration to a multi-dimensional spatial arrangement. This dimensional change reduces the loop area and parasitic inductance, thereby reducing impedance effects while supporting high-frequency switching operations
2Reliability
If conventional conductive buses are used, then electrical connectivity is established, but oscillation and system performance degradation occur due to impedance effects
Solution Approach 1:
The electrical connection is segmented into multiple planar bus sections connected in series, which distributes the current flow and reduces peak impedance effects. This segmentation stabilizes the electrical connection by preventing oscillations that would occur with conventional single-piece buses
Solution Approach 2:
The offset parallel plane structure acts as an intermediary between the semiconductor switching devices and the conventional bus configuration. This intermediate structure reduces impedance effects and stabilizes the electrical connection, preventing oscillation while maintaining proper electrical connectivity
Data Source
AI summary
A bus assembly includes a planar first bus, a second bus including a first planar bus section on the first bus and a second planar bus section connected to the first planar bus section and offset from the first planar bus section, and a third bus comprising a third planar bus section disposed between the first bus and the second planar bus section, and a fourth planar bus section connected to the third planar bus section, offset from third planar bus section, and disposed on the first planar bus section.