Offset Power Tile Die Structure for Vertical Resistance Reduction
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Solution Overview
Problem
The distribution of power within semiconductor devices affects their performance in terms of frequency and power, with existing technologies struggling to manage transient droop and active power dissipation effectively.
Innovation Solution
A die configuration with offset arrays of power tiles and mesh segments, connected by vias and power rails, allowing for reduced vertical resistance and efficient signal propagation, which includes generating specific metal layers with power tiles, mesh segments, and power rails configured to different voltages, and using zipper structures to facilitate connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power tiles are arranged in a grid pattern with power rails, then power distribution is achieved, but vertical resistance increases and signal propagation efficiency decreases
Solution Approach 1:
The patent transitions from a two-dimensional grid arrangement to a three-dimensional stacked arrangement where power tiles are vertically offset between layers. This dimensional change allows power signals to propagate through multiple layers via vias, reducing vertical resistance by providing multiple parallel conduction paths and shorter current paths compared to traditional planar layouts.
Solution Approach 2:
The patent implements nested power distribution by placing power tiles of different voltages within enclosed regions formed by power rails and mesh segments. First power tiles are enclosed by first power rails and first mesh segments, while second power tiles are enclosed by second power rails and second mesh segments, creating a nested hierarchical structure that optimizes power delivery to different functional blocks.
2Reliability
If power tiles are arranged in a grid pattern with power rails, then power distribution is achieved, but signal propagation efficiency decreases
Solution Approach 1:
The three-dimensional stacked arrangement enables signals to propagate vertically through offset power tiles via direct via connections rather than traversing long horizontal paths through power rails. This reduces signal propagation delay by providing shorter, more direct current paths and enabling parallel signal transmission through multiple vertical channels.
Solution Approach 2:
The patent segments the power distribution network into multiple independent voltage domains with offset power tiles for different voltages. Each voltage domain has its own enclosed region with power rails and mesh segments, allowing independent optimization of signal paths for each voltage level and reducing signal interference between different voltage domains.
3Object-affected harmful factors
If offset arrays of power tiles are used, then vertical resistance is reduced, but device complexity increases
Solution Approach 1:
The patent employs universal power rail and mesh segment structures that serve multiple functions: they enclose power tiles of different voltages, provide power distribution paths, and form boundaries for different voltage domains. The offset arrangement of power tiles across layers is achieved using the same basic power rail and via structures, reducing the need for additional specialized components and simplifying manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces vertical resistance and enhances signal propagation efficiency, ensuring sufficient voltage for correct transistor operation and improved semiconductor device performance.
Implementation Method 1
a first plurality of vias operatively connecting the first power rail with the first plurality of power mesh segments and the first plurality of power tiles
Data Source
AI summary
A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.