LO Divider Phase Synchronization Using Offset Voltage Preset

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In multiple-input multiple-output (MIMO) systems, the phase ambiguity of divider circuits is not synchronized when enabled and disabled, leading to inefficiencies in power consumption and synchronization time, as they must be continuously enabled to maintain synchronization.

Innovation Solution

A method and system that synchronizes the phase of output signals from multiple frequency divider circuits by adding a predetermined offset voltage before enabling them, using a local-oscillator (LO) buffer to initiate frequency division, and then removing the offset voltage to allow the divider circuits to drive other circuits without continuous enablement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If divider circuits are continuously enabled to maintain phase synchronization, then phase synchronization is maintained, but power consumption increases

Engineering Contradiction:
Improvephase synchronizationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by adding an offset voltage to the divider circuits before enabling them. This pre-conditioning ensures that when the dividers are enabled, they start with a known phase relationship, eliminating the need for continuous operation to maintain synchronization. The offset voltage is added in advance, allowing the circuits to be enabled only when needed while maintaining phase coherence.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic action by enabling and disabling the divider circuits only when required, rather than keeping them continuously enabled. The circuits are enabled periodically when phase synchronization is needed, and disabled otherwise to save power. This periodic enablement strategy, combined with the offset voltage technique, maintains synchronization while reducing overall power consumption.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If divider circuits are enabled and disabled to reduce power consumption, then power consumption decreases, but phase synchronization is lost

Engineering Contradiction:
Improvepower consumptionVSAvoidphase synchronization
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The offset voltage is applied as a preliminary action before enabling the divider circuits. This pre-conditioning establishes a known phase relationship in advance, so when the circuits are enabled after being disabled, they maintain synchronization without requiring continuous operation. The preliminary offset voltage application ensures phase coherence is preserved across enable/disable cycles.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If loopback mechanism is used for phase ambiguity calibration, then phase calibration is achieved, but time and power consumption increase

Engineering Contradiction:
Improvephase calibrationVSAvoidcalibration time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The offset voltage technique serves as a preliminary action that pre-establishes phase relationships before the divider circuits are enabled. This preliminary phase setting eliminates or reduces the need for subsequent loopback calibration mechanisms, saving both time and power that would otherwise be required for phase ambiguity calibration.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8704559B2Method and system for synchronizing the phase of a plurality of divider circuits in a local-oscillator signal path
Publication Date: 2014.04.22 MEDIATEK SINGAPORE PTE LTD
  • US8704559B2 patent drawing
  • US8704559B2 patent drawing
  • US8704559B2 patent drawing

AI summary

A method and system for synchronizing the output signal phase of a plurality of frequency divider circuits in a local-oscillator (LO) or clock signal path is disclosed. The LO path includes a plurality of frequency divider circuits and a LO buffer for receiving a LO signal coupled to the plurality of frequency divider circuits. The method and system comprise adding offset voltage and setting predetermined state to each of the frequency divider circuits; and enabling the frequency divider circuits. The method and system includes enabling the LO buffer to provide the LO signal to the frequency divider circuits after they have been enabled. When the LO signal drives each of the frequency divider circuits, each of the frequency divider circuits starts an operation. Finally the method and system comprise removing the offset voltage from each of the frequency divider circuits to allow them to effectively drive other circuits.