CMOS Image Sensor ADC Using Offset Ramps for Faster CMS Readout

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Solution Overview

Problem

Conventional CMOS image sensors face increased total analog-digital conversion time when using the Correlated Multiple Sampling (CMS) technique due to repeated analog-digital conversion operations with the same ramp signal, leading to noise in low-illumination environments.

Innovation Solution

An analog-digital converter that employs a ramp signal selection unit to choose ramp signals with different offsets, a comparison unit to compare pixel signals with selected ramp signals, and a counting unit to count clock cycles until transition, allowing simultaneous analog-digital conversions using ramp signals that decrease with the same slope, thereby reducing overall conversion time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the CMS technique is applied using the same ramp signal for repeated analog-digital conversions, then noise is reduced in low-illumination environments, but the total analog-digital conversion time increases significantly

Engineering Contradiction:
Improveimage qualityVSAvoidtotal analog-digital conversion time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the single ramp signal into multiple ramp signals with different offsets. Instead of performing M sequential conversions with one ramp signal, the system segments the conversion process by preparing multiple ramp signals (RAMP1, RAMP2, ..., RAMPM) that can be used simultaneously or in parallel, thereby reducing the total conversion time while maintaining noise reduction benefits

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent prepares multiple ramp signals with different offsets in advance before the analog-digital conversion process begins. This preliminary preparation allows the system to immediately perform multiple conversions without waiting for sequential completion, thus reducing the overall conversion time while still enabling correlated multiple sampling for noise reduction

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If multiple analog-digital conversion operations are performed sequentially using the same ramp signal, then the conversion is completed accurately, but the conversion process takes longer

Engineering Contradiction:
Improveconversion accuracyVSAvoidconversion speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent merges multiple conversion operations by using multiple ramp signals simultaneously. Instead of completing one conversion at a time with a single ramp signal, the system combines multiple conversion operations that proceed in parallel using different ramp signals, thereby improving productivity while maintaining measurement precision through the correlated sampling process

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the analog-digital converter waits for one conversion to complete before starting the next, then each conversion is processed thoroughly, but the overall processing time increases

Engineering Contradiction:
Improveconversion reliabilityVSAvoidconversion duration
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent enables continuous useful action by preparing multiple ramp signals in advance and using them for simultaneous or parallel conversions. This eliminates idle waiting time between conversions, as the system can continuously process multiple signals without interruption, thereby reducing the overall conversion duration while maintaining reliability through the correlated sampling methodology

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS10306171B2Analog-digital converter, readout circuit and CIS including the same
Publication Date: 2019.05.28 SK HYNIX INC
  • US10306171B2 patent drawing
  • US10306171B2 patent drawing
  • US10306171B2 patent drawing

AI summary

An analog-digital converter may include: an analog-digital converter comprising: a ramp signal selection unit suitable for receiving ramp signals having different offsets, and sequentially selecting one of the ramp signals according to a preset order; a comparison unit suitable for comparing the magnitudes of the selected ramp signal with a pixel signal, and outputting a comparison signal according to the comparison result; and a counting unit suitable for counting the number of clocks of a clock signal until the comparison signal transitions, and outputting a count signal based on the count when the comparison signal transitions.