Offset Source-Drain Structure for Transistor Uniformity
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Solution Overview
Problem
The reverse narrow channel effect in transistors, caused by reduced gate length and device region width, leads to non-uniform threshold values and degradation of transistor characteristics, particularly due to the concentration of electric fields and charge accumulation in the device isolation insulating film, making it challenging to maintain transistor performance while reducing chip size.
Innovation Solution
A semiconductor device structure where the source and drain regions are offset from the device isolation insulating film, with first and second gate electrode extension portions covering the end portions of these regions, preventing electric field concentration and charge accumulation, and allowing for uniform channel profiles even with polysilazane as the insulating film material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate length and device region width of the transistor are decreased to reduce chip size, then the integration density increases, but the threshold value becomes non-uniform and transistor characteristics deteriorate due to reverse narrow channel effect
Solution Approach 1:
The patent applies local quality by creating an offset structure specifically at the corner portions of the device region where it intersects with the device isolation insulating film. The active region is recessed by a first offset distance from the device isolation insulating film, and the gate electrode is further offset by a second offset distance, creating a localized structural modification at critical areas to suppress electric field concentration and maintain uniform threshold values across the transistor channel.
2Reliability
If additional processes such as ion implantation are performed specifically for peripheral transistors to improve characteristics, then transistor characteristics can be maintained, but the number of processes increases and manufacturing cost rises
Solution Approach 1:
The patent merges the peripheral transistor structure with the memory cell structure by using the same offset-based design. The active region offset and gate electrode offset structures are applied uniformly to both peripheral transistors and memory cells, allowing both to be fabricated using the same process steps without requiring additional ion implantation or specialized processing for peripheral devices.
Data Source
AI summary
A semiconductor device includes a device isolation insulating film which is buried in a semiconductor substrate, a gate insulation film which is provided on the semiconductor substrate, a gate electrode which is provided on the gate insulation film, a source region and a drain region which are provided in the semiconductor substrate and spaced apart from each other in a manner to sandwich the gate electrode, both end portions of each of the source region and the drain region being offset from the device isolation insulating film in a channel width direction by a predetermined distance, and first and second gate electrode extension portions which are provided in a manner to cover both end portions of each of the source region and the drain region in a channel length direction.