Offset Spacer Formation Using Etch Stop Layer
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Solution Overview
Problem
The formation of offset spacers in semiconductor devices leads to a short channel effect and non-uniform impurity concentration in lightly-doped drain (LDD) regions due to by-products from the etching process, which hinders the control of threshold voltages and junction depth.
Innovation Solution
A method involving the formation of an etch stop layer of silicon nitride or silicon oxynitride between the gate electrode and the first spacer, followed by the sequential stacking of a first spacer layer and a re-oxidation layer, which allows for controlled etching and prevents substrate recession, enabling uniform impurity distribution in LDD regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an offset spacer is formed by anisotropically etching a spacer layer, then the short channel effect is reduced, but by-products adhere to the semiconductor substrate causing non-uniform impurity concentration in LDD regions
Solution Approach 1:
A cleaning layer is introduced as an intermediary between the spacer layer and the semiconductor substrate. This cleaning layer captures by-products during anisotropic etching, preventing them from adhering to the substrate and contaminating subsequent LDD regions, thereby resolving the contradiction between achieving offset spacer formation and maintaining impurity concentration uniformity
Solution Approach 2:
The harmful by-products are extracted from the critical fabrication area by transferring them to the cleaning layer. The cleaning layer is specifically designed to absorb and retain these by-products, removing them from the path of subsequent ion implantation processes and ensuring uniform LDD region formation
2Productivity
If transistor size is reduced to achieve higher integration, then integration density increases, but short channel effect worsens
Solution Approach 1:
The solution moves from two-dimensional scaling to three-dimensional structural modification by forming offset spacers that extend vertically from the gate electrode sidewalls. This adds a vertical dimension to the device structure, effectively increasing the channel length without increasing the planar footprint, thus maintaining high integration density while mitigating short channel effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures a uniform impurity concentration in LDD regions and improved control over threshold voltages, reducing the short channel effect and maintaining the effective channel length, thus enhancing the electrical characteristics of semiconductor devices.
Implementation Method 1
An etch stop layer may be formed on the semiconductor substrate and the gate electrode, wherein the etch stop layer includes a nitride
Implementation Method 2
An offset spacer may be formed by anisotropically etching the spacer layer
Implementation Method 3
the polysilicon re-oxidation layer may be formed by a thermal oxidation method
Data Source
AI summary
A method of forming a semiconductor device having an offset spacer may include forming a gate electrode on a semiconductor substrate. An etch stop layer including a nitride may be formed on the entire surface of the semiconductor substrate having the gate electrode. First spacers may be formed on the sidewalls of the gate electrode. The first spacers may be formed of a material layer having an etch selectivity with respect to the etch stop layer. The etch stop layer may be exposed on the semiconductor substrate on both sides of the gate electrode. Lightly-doped drain (LDD) regions may be formed in the semiconductor substrate using the gate electrode and the first spacers as an ion implantation mask. Second spacers may be formed on the first spacers. Accordingly, a semiconductor device having an offset spacer may be provided.