Offset-Stacked Semiconductor Package With Stable Wire Bonding
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Solution Overview
Problem
The challenge lies in developing semiconductor packages that are compact, high-performance, and structurally stable while integrating multiple semiconductor chips, as existing technologies struggle to reduce size and improve electrical characteristics.
Innovation Solution
A semiconductor package design featuring offset stacking of semiconductor chips with bonding wires connecting them in a specific configuration, including a substrate with offset semiconductor chips and bonding wires, and a mold layer covering the chips and wires to enhance structural stability and reduce size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple semiconductor chips are stacked vertically to reduce package size, then the package footprint is reduced, but structural stability deteriorates due to height reduction and offset arrangement
Solution Approach 1:
The patent transitions from a conventional planar arrangement to a three-dimensional offset stacking configuration. Chips are arranged in multiple layers with horizontal offsets, utilizing vertical and diagonal dimensions to reduce the package footprint while maintaining structural integrity through spatial optimization.
Solution Approach 2:
The patent employs asymmetric offset positioning of chips in the stacked arrangement. Instead of symmetric alignment, each chip is horizontally offset from the previous layer, creating an asymmetric configuration that reduces the overall package area while maintaining structural stability through distributed weight and optimized bonding wire routing.
2Volume of stationary object
If bonding wires are routed through offset chip configurations to achieve compactness, then package size is reduced, but wire length and complexity increase
Solution Approach 1:
The bonding wire configuration is segmented into distinct sections: vertical segments connecting chips within the same column, and diagonal segments connecting chips across different columns and layers. This segmentation allows for systematic routing that reduces overall wire length while managing complexity through modular connection patterns.
Solution Approach 2:
The patent applies different bonding wire routing strategies to different regions of the package. Chips in the same column use direct vertical bonding, while chips in different columns use diagonal bonding paths. This local optimization minimizes wire length in each region while managing overall complexity.
3Stability of the object's composition
If chip pads are spaced apart to accommodate offset stacking, then structural stability is improved, but electrical connectivity complexity increases
Solution Approach 1:
The bonding wires serve multiple functions simultaneously: they provide electrical connectivity between chip pads and act as structural support elements in the offset stacking configuration. This multi-functionality allows the same component to address both electrical connectivity requirements and structural stability without increasing overall system complexity.
Data Source
AI summary
A semiconductor package may include a substrate, a first chip on the substrate, a second chip stacked on and offset from the first chip in a first direction, a third chip stacked on and offset from the second chip in a second direction opposite to the first direction, a first bonding wire connecting the substrate to the first chip, and a second bonding wire connecting the first chip to the third chip. The first chip may include a first chip pad disposed on a top surface of the first chip and spaced apart from the second chip in the second direction. The third chip may include a second chip pad disposed on a bottom surface of the third chip and spaced apart from the second chip in the second direction. The second chip pad may be placed above the first chip pad.