Offset-Stacked Semiconductor Package for Reliable Multi-Chip I/O
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high integration and reliable connection of multiple semiconductor chips while maintaining seed layer quality and minimizing manufacturing defects.
Innovation Solution
A semiconductor package design involving offset-stacked semiconductor chips with conductive posts and adhesive layers, surrounded by molding layers and a redistribution structure, which enhances connectivity and reduces manufacturing defects through precise alignment and adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked to increase integration, then the number of I/O connection terminals increases, but manufacturing defects increase and seed layer quality deteriorates
Solution Approach 1:
The patent divides the conductive posts into multiple segments (first conductive posts, second conductive posts, third conductive posts) arranged at different heights and positions. This segmentation allows each chip to be connected to multiple conductive posts at different levels, distributing the connection load and reducing stress on any single connection point, thereby maintaining connection reliability while increasing the number of I/O terminals.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked arrangement with conductive posts at multiple heights. The first, second, and third conductive posts are positioned at different vertical levels, creating a multi-layer connection structure that increases I/O capacity without compromising connection reliability through proper spatial distribution.
2Quantity of substance
If multiple semiconductor chips are stacked to increase integration, then the number of I/O connection terminals increases, but manufacturing precision decreases
Solution Approach 1:
The patent employs adhesive layers (first adhesive layer, second adhesive layer, third adhesive layer) that are applied in advance to the carrier substrate and between chips before the stacking process. These pre-applied adhesive layers provide precise positioning and alignment features that guide the placement of each chip and conductive post assembly, ensuring manufacturing precision is maintained throughout the multi-chip stacking process.
Solution Approach 2:
The adhesive layers serve as intermediary elements between the carrier substrate, chips, and conductive posts. These adhesive layers facilitate precise alignment and secure bonding, acting as mediators that enable the complex multi-chip stacking process to maintain high manufacturing precision despite the increased complexity of multiple I/O terminals.
3Device complexity
If conductive posts are placed close to chips for compact design, then device complexity reduces, but seed layer quality deteriorates
Solution Approach 1:
The patent applies different properties to different regions: the first adhesive layer has enhanced adhesion properties in the region where it contacts the carrier substrate and first conductive posts, while the second and third adhesive layers provide similar functionality for subsequent chips. This localized optimization of adhesive properties ensures seed layer quality is maintained in critical regions while allowing compact overall design.
Solution Approach 2:
The adhesive layers act as intermediary buffers between the conductive posts and chips, allowing the conductive posts to be positioned close to chips for compact design while the adhesive layer protects the seed layer quality by providing a controlled interface that prevents direct harmful interactions between conductive posts and chip structures.
Data Source
AI summary
Provided is a semiconductor package including a first semiconductor chip; a plurality of lower first conductive posts on the first semiconductor chip; a second semiconductor chip offset-stacked on the first semiconductor chip; a plurality of lower second conductive posts on the second semiconductor chip; a first molding layer around the first semiconductor chip, and the second semiconductor chip; a third adhesive layer on an upper surface of the first molding layer; a plurality of upper first conductive posts on the plurality of lower first conductive posts; a plurality of upper second conductive posts on the plurality of lower second conductive posts; a third semiconductor chip on the third adhesive layer; a plurality of third conductive posts on the third semiconductor chip; a second molding layer on the third adhesive layer; and a redistribution structure on the second molding layer.