Offset-Stacked Semiconductor Package for Dense Chip Interconnection
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Solution Overview
Problem
The challenge of attaching a high number of solder balls to miniaturized semiconductor chips and handling them for testing becomes difficult, and changing boards to accommodate varying chip sizes is complex, hindering the development of compact and high-performance semiconductor packages.
Innovation Solution
A semiconductor package design featuring offset stacking of semiconductor chips with inclined insulating patterns and conductive posts, encapsulated by mold layers and passivation layers, allowing for efficient vertical interconnections and robust support through conductive posts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the semiconductor chip is reduced to increase integration density, then the number of chips per package increases, but it becomes increasingly difficult to attach a high number of solder balls to the chip and to handle and test the solder balls
Solution Approach 1:
The patent transitions from a conventional single-layer chip arrangement to a three-dimensional stacked configuration with multiple chip layers (first chip layer, second chip layer) vertically arranged. This dimensional change allows increased integration density without proportionally increasing the number of solder balls per chip, as inter-layer connections are established through vertical vias and conductive structures rather than extensive surface mounting.
Solution Approach 2:
The patent implements a nested structure where multiple chip layers are stacked vertically with each layer containing chips that are horizontally offset. The first chip layer and second chip layer are nested in space, with conductive posts and insulating patterns nested within the stack structure. This nesting approach maximizes space utilization and reduces the overall package footprint while maintaining manageable solder ball counts per individual chip.
2Quantity of substance
If the size of the semiconductor chip is reduced, then integration density increases, but it is necessary to change a board in accordance with a size of a semiconductor chip, which is difficult
Solution Approach 1:
The patent creates a universal package structure that can accommodate different chip sizes and configurations through the standardized stacked architecture. The first and second chip layers can contain varying numbers and sizes of chips while maintaining the same overall package footprint and connection interface. This multi-functional design allows the same board layout to support different integration densities without requiring board changes.
Solution Approach 2:
By moving to a three-dimensional stacked configuration, the patent decouples the relationship between chip size and package footprint. Different chip sizes can be accommodated within the vertical stack without changing the horizontal board dimensions, as the integration density is achieved through vertical stacking rather than horizontal expansion.
3Stability of the object's composition
If offset stacking of semiconductor chips is implemented, then vertical interconnections are enabled and structural stability is improved, but the manufacturing process becomes more complex with multiple layers and conductive posts
Solution Approach 1:
The patent employs preliminary action by forming insulating patterns with inclined surfaces before mounting the chips. These pre-formed insulating structures facilitate subsequent chip placement and conductive post formation by providing built-in alignment guides and spacing structures. The inclined surfaces of the insulating patterns are prepared in advance to receive and properly position the offset-stacked chips.
Solution Approach 2:
The patent introduces intermediary structures including insulating patterns and conductive posts that mediate between the offset-stacked chips. The insulating patterns with inclined surfaces act as intermediaries that facilitate the connection between chips at different levels, while conductive posts serve as intermediary conductive elements that establish electrical connections through the insulating layers without requiring direct chip-to-chip contact.
Data Source
AI summary
Example embodiments are directed to a semiconductor package including a first structure having a second semiconductor chip on a first semiconductor chip and horizontally offset from the first semiconductor chip in a first direction, and a first insulating pattern covering side surfaces of the first semiconductor chip. A width of the first insulating pattern decreases in a direction from a lower surface of the first semiconductor chip toward an upper surface of the first semiconductor chip. The semiconductor package further comprises a first mold layer surrounding the first semiconductor chip, the second semiconductor chip, and the first insulating pattern, a first conductive post that vertically penetrates the first mold layer and coupled to the upper surface of the first semiconductor chip, and a second conductive post coupled to an upper surface of the second semiconductor chip and exposed through an upper surface of the first mold layer.