Offset Stacked IC Package Eliminating Wire Loops
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Solution Overview
Problem
Existing integrated circuit package technologies face challenges in reducing package dimensions, increasing manufacturing yield, and lowering costs while accommodating more integrated circuits in a shrinking physical space, as they struggle with space requirements for electrical connections and spacers that increase manufacturing costs and limit height reduction.
Innovation Solution
A stacked integrated circuit package-in-package system is developed, featuring a substrate with offset configurations and internal interconnects that eliminate the need for wire loops and top surface contacts, allowing for a more compact design with encapsulation that reduces package height and maintains connectivity through bottom contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spacers or interposers are used to connect stacked integrated circuits, then electrical connections are established, but manufacturing cost increases and manufacturing yield decreases
Solution Approach 1:
The patent extracts and eliminates the spacer or interposer component from the stacked integrated circuit structure. By directly connecting the first and second integrated circuits without these intermediate elements, the invention removes the sources of manufacturing complexity and cost while maintaining electrical connectivity through direct bonding or wire bonding between the circuits themselves.
Solution Approach 2:
The patent merges the functions of multiple components (spacer, interposer, and electrical connection) into a single integrated structure. The substrate integrates both mechanical support and electrical connection functions, eliminating the need for separate spacer or interposer components and thereby reducing manufacturing steps, cost, and improving yield.
2Reliability
If spacers or interposers are used to connect stacked integrated circuits, then electrical connections are established, but the number of manufacturing steps increases
Solution Approach 1:
The patent removes the spacer or interposer from the stacked circuit architecture, thereby reducing the number of manufacturing steps required. Direct bonding or wire bonding between integrated circuits eliminates the need for separate spacer fabrication, alignment, and attachment processes.
Solution Approach 2:
The substrate is designed to integrate both mechanical support and electrical connection functions, merging multiple components into one. This integration reduces the overall number of manufacturing steps and simplifies the fabrication process while maintaining reliable electrical connections between stacked circuits.
3Reliability
If wire loops for bond wires are used for electrical connections, then connectivity is achieved, but package space requirements increase
Solution Approach 1:
The patent transitions from planar wire loop connections to vertical or three-dimensional interconnect structures. By using through-substrate vias, bump bonds, or other vertical connection methods, the invention achieves electrical connectivity without requiring the lateral space needed for wire loops, thereby reducing package footprint.
Solution Approach 2:
The patent replaces the mechanical wire loop bonding system with alternative connection methods such as direct semiconductor bonding, bump bonding, or through-substrate vias. These methods require minimal or no lateral space compared to wire loops, thereby reducing the overall package area while maintaining reliable electrical connectivity.
4Ease of manufacture
If conventional packaging technologies are used, then manufacturing is simplified, but package dimensions cannot be reduced
Solution Approach 1:
The patent adopts a vertical stacking architecture where integrated circuits are stacked in the z-dimension rather than being arranged laterally in the x-y plane. This dimensional transition enables miniaturization of the package footprint while maintaining manufacturing simplicity through established vertical bonding and encapsulation processes.
Solution Approach 2:
The patent implements a package-in-package structure where one integrated circuit is nested within or directly bonded to another, with both housed within a single encapsulation. This nesting approach reduces overall package dimensions while using conventional manufacturing techniques for encapsulation and bonding.
Data Source
AI summary
A stacked integrated circuit package-in-package system is provided including forming a substrate having a top surface and a bottom surface, mounting a first device over the top surface, stacking a second device over the first device in an offset configuration, connecting a first internal interconnect between the first device and the bottom surface, connecting a second internal interconnect between the second device and the bottom surface, and encapsulating the first device and the second device.