Offset Stacked Memory Chips with Nested Controller
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in reducing package size and thickness while maintaining increased storage capacity, as conventional configurations either increase horizontal size or fail to adequately decrease thickness when attempting to minimize package size.
Innovation Solution
A semiconductor memory device configuration where a stack of memory chips is juxtaposed with a memory controller chip on a substrate, with the upper memory chip shifted towards the mounting position of the memory controller chip, allowing part of the controller chip to be housed within the space between the substrate and the protruding stack memory chip, thereby reducing package size and thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a plurality of memory chips is stacked and a memory controller chip is then stacked on the stack of memory chips, then the horizontal size of the package is reduced, but the thickness of the package cannot be reduced
Solution Approach 1:
The memory controller chip is nested within the space created by the offset stacking of memory chips. Specifically, the upper memory chip is stacked to shift toward the mounting position of the memory controller chip, creating a recess space between the substrate and the protruding part of the stack memory chip. The memory controller chip is then mounted within this recess space, effectively hiding it within the overall package footprint and reducing both horizontal size and thickness.
Solution Approach 2:
The invention transitions from a traditional planar arrangement to a three-dimensional offset stacking configuration. By stacking memory chips with horizontal offsets rather than perfect alignment, the design creates vertical recess spaces that allow the memory controller chip to be positioned in a different spatial dimension, simultaneously reducing horizontal footprint and package thickness.
2Length of stationary object
If the stacked memory chips and the memory controller chip are mounted side by side, then the thickness of the package is reduced, but the horizontal size of the package increases
Solution Approach 1:
The memory controller chip is nested within the recess space formed by the offset stacking configuration. The upper memory chip protrudes toward the mounting position of the memory controller chip, creating a hollow space between the substrate and the protruding part. This allows the memory controller chip to be positioned within the horizontal footprint of the stack memory chip, reducing the overall horizontal package size while maintaining thin profile.
Solution Approach 2:
The invention merges the spatial occupation of the memory controller chip with the recess space of the stack memory chip. Instead of requiring separate horizontal space for the controller chip, the offset stacking design allows the controller to be positioned within the unused space created by the offset configuration, effectively combining the footprints of multiple components into a smaller overall package area.
Data Source
AI summary
An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip adjacent the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.