Offset Stacked Memory Chips via Solder Bumps
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in efficiently stacking memory chips with high capacity and small size, often requiring costly through-silicon via processes and wire bonding, which can increase manufacturing costs and limit thinning capabilities.
Innovation Solution
A semiconductor package design featuring a logic chip on a substrate with offset memory chips connected via solder bumps and redistribution lines, eliminating the need for through-silicon via processes and wire bonding, allowing for efficient signal transmission and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon via processes and wire bonding are used to stack memory chips, then reliable electrical connection is achieved, but manufacturing cost increases and thinning capability is limited
Solution Approach 1:
The patent extracts and eliminates the through-silicon via process from the semiconductor packaging structure. By using a build-up layer with conductive patterns instead of penetrating vias through the substrate, the design removes the complex and costly TSV fabrication steps while maintaining reliable electrical connections between stacked memory chips.
Solution Approach 2:
The patent introduces a build-up layer as an intermediary structure between the substrate and memory chips. This build-up layer contains conductive patterns that serve as the mediation pathway for electrical signals, replacing the need for direct through-silicon via connections and wire bonding, thereby simplifying the manufacturing process.
2Reliability
If through-silicon via processes and wire bonding are used to stack memory chips, then reliable electrical connection is achieved, but package thickness increases
Solution Approach 1:
The patent extracts the through-silicon via process from the structure, eliminating the need for deep via formation and associated support structures. This extraction allows for a thinner overall package design while maintaining reliable electrical connections through the simplified build-up layer approach.
3Quantity of substance
If memory chips are stacked with traditional methods, then high capacity is achieved, but charge transmission efficiency decreases
Solution Approach 1:
The build-up layer with optimized conductive patterns serves as an efficient intermediary for charge transmission. This structure provides low-resistance pathways for electrical signals between stacked memory chips, reducing energy loss and improving charge transmission efficiency compared to traditional TSV and wire bonding methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances charge transmission efficiency and fill factor while reducing manufacturing costs and enabling thinner packages by eliminating the need for costly processes, thus addressing the challenges of high-capacity and small-sized semiconductor devices.
Implementation Method 1
The first active surface and the second active surface may oppose each other and may be operatively connected to each other through a first solder bump
Data Source
AI summary
A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.