Offset-Stacked Semiconductor Package for Shorter Bonding Wires
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Solution Overview
Problem
Multi-chip semiconductor packages face challenges in reducing the length of bonding wires, which affects signal processing speed and package thickness.
Innovation Solution
A semiconductor package design with offset stacking and dummy bonding pads that utilize shorter bonding wires by connecting upper bonding pads to substrate pads via lower dummy bonding pads, optimizing the layout of bonding pads and wires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If chips are stacked in a conventional aligned manner, then the package structure is simple, but the bonding wire length becomes excessive
Solution Approach 1:
The patent transitions from conventional aligned stacking to offset stacking, where chips are positioned at different lateral positions in the vertical stack. This dimensional change in chip arrangement allows bonding wires to connect to exposed bonding pads on lower chips, significantly reducing wire length while the offset pattern manages the structural complexity
Solution Approach 2:
The patent introduces dummy bonding pads as intermediary elements on chip surfaces. These dummy pads serve as intermediate connection points that enable shorter bonding wire paths by providing accessible bonding locations closer to the connection target, effectively mediating the connection between upper chip bonding pads and lower chip bonding pads
2Speed
If bonding wire length is reduced, then signal processing speed improves, but package thickness must be precisely controlled
Solution Approach 1:
The patent systematically varies the offset distances between stacked chips and the positions of bonding pads to optimize bonding wire length. By adjusting these geometric parameters, the design achieves shorter wire lengths for faster signal processing while controlling the overall package thickness through precise parameter selection
3Length of moving object
If offset stacking is implemented to reduce bonding wire length, then more bonding pads are exposed, but the layout complexity increases
Solution Approach 1:
The patent divides the chip stack into segments with different offset patterns, where each segment exposes specific bonding pads strategically. This segmentation allows selective exposure of bonding pads at different lateral positions, reducing wire length for critical connections while managing overall layout complexity through organized segmentation
Data Source
AI summary
A semiconductor package includes a package substrate having a first side portion adjacent to a first edge, and a second side portion adjacent to a second edge opposite the first edge; a plurality of first substrate pads on the package substrate at the first side portion of the package substrate; a first chip on the package substrate; a second chip stacked on the first chip in a step-wise manner to result in a first exposure region exposing a portion of a surface of the first chip with respect to the second chip due to the step-wise stacking, the first exposure region being adjacent to a first edge of the first chip; a plurality of first bonding pads on a first portion of the first exposure region, the first portion of the first exposure region being adjacent to the first edge of the first chip; a plurality of second bonding pads on a second portion of the first exposure region, the second portion of the first exposure region further from the first edge of the first chip than the first portion of the first exposure region is to the first edge of the first chip, the plurality of second bonding pads being electrically insulated from any circuit components in the first chip; a plurality of third bonding pads on a surface of the second chip; and a plurality of bonding wires electrically connecting the third bonding pads to the first substrate pads via the second bonding pads.