Offset-Stacked Semiconductor Package for Dense Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in integrating highly integrated semiconductor chips with a sufficient number of connection terminals while ensuring reliable connections and compact design.
Innovation Solution
A semiconductor package design featuring an offset-stacked semiconductor chip configuration with a redistribution structure, conductive posts, and molding layers, where the width of the posts and molding layers are carefully managed to ensure efficient electrical connections and compact integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are highly integrated with increased number of connection terminals, then connection density and functionality are improved, but package size and complexity increase
Solution Approach 1:
The patent implements a 3D stacked chip architecture where multiple semiconductor chips are vertically stacked and interconnected through conductive posts. This vertical stacking approach transitions from a 2D planar layout to a 3D volumetric structure, enabling increased connection terminals and integration density without proportionally increasing the package footprint area.
Solution Approach 2:
The patent employs nested molding layers (first lower molding layer, second lower molding layer, upper molding layer) that encapsulate and protect the stacked chips and conductive structures. The molding layers are arranged in nested configurations where inner layers protect core components while outer layers provide additional protection and structural support, maximizing space utilization within the package.
2Quantity of substance
If offset-stacked chip configuration is used to increase integration density, then connection density is improved, but manufacturing precision and alignment requirements increase
Solution Approach 1:
The patent introduces molding layers as intermediary structures between the offset-stacked chips. These molding layers provide mechanical support, stress relief, and alignment tolerance compensation, enabling the offset stacking configuration without requiring extremely tight alignment precision between chips. The molding material fills gaps and accommodates minor misalignments while maintaining structural integrity.
3Reliability
If conductive posts with optimized width are used, then electrical connection efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different width specifications for conductive posts at different locations and functions. The conductive posts have optimized width dimensions tailored to their specific electrical connection requirements, with wider posts for high-current paths and narrower posts for signal connections. This localized optimization of post dimensions improves electrical connection efficiency while managing overall manufacturing complexity through standardized fabrication processes.
Data Source
AI summary
Provided is a semiconductor package including a redistribution structure, a first chip structure on the redistribution structure and including a first lower semiconductor chip, a second lower semiconductor chip on the first lower semiconductor chip, and a first lower molding layer, a second lower molding layer on the first chip structure, a plurality of conductive posts penetrating the second lower molding layer, and a second chip structure on the first chip structure and the plurality of conductive posts and including a first upper semiconductor chip, a first upper chip post extending from the first upper semiconductor chip, a second upper semiconductor chip on the first upper semiconductor chip, a second upper chip post extending from the second upper semiconductor chip, and an upper molding layer, wherein a width of the first upper chip post is less than a width of the plurality of conductive posts in a horizontal direction.