Offset-Stacked Semiconductor Package for Peeling and Impedance Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multi-chip semiconductor packages, interfacial peeling failures occur due to impedance mismatch and hygro-mechanical stress between the molding layer and chips, especially in high-temperature and high-humidity environments, caused by differences in hygro-swelling expansion.
Innovation Solution
A semiconductor package design with offset stacking of chips and a molding member that reduces the volume overhang region, using bonding wires for chip-to-chip connections to minimize impedance mismatch and enhance electrical characteristics, and a molding member that covers the chips to prevent peeling failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If molding member occupancy ratio on first-stage chip is high, then chip-to-chip bonding is effective for impedance matching, but occupied volume ratio increases causing peeling at corner of overhang portion
Solution Approach 1:
The patent segments the chip groups into two categories with different offset orientations. The first group maintains bonding for impedance matching, while the second group uses offset arrangement to reduce molding member volume occupancy, thereby preventing peeling at overhang corners without compromising electrical performance.
Solution Approach 2:
Different offset strategies are applied to different chip groups based on their specific requirements. The first group uses bonding-oriented arrangement for electrical performance, while the second group uses volume-reduced arrangement for mechanical reliability, achieving local optimization of both impedance matching and peeling prevention.
Data Source
AI summary
A semiconductor package includes a package substrate, a first group of semiconductor chips disposed on the package substrate and including at least two lower semiconductor chips that are sequentially stacked and are offset in a first horizontal direction, a second group of semiconductor chips stacked on the first group of semiconductor chips and including at least two upper semiconductor chips that are sequentially stacked and are offset in a direction opposite to the first horizontal direction, first bonding wires electrically connecting the chip pads of the first group of semiconductor chips to first substrate pads of the package substrate, second bonding wires electrically connecting the chip pads of the second group of semiconductor chips to second substrate pads of the package substrate and a molding member covering the first group of semiconductor chips and the second group of semiconductor chips on the package substrate.