Offset-Stacked Semiconductor Package With Interconnection Layer Routing
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high integration density and improved electrical characteristics while maintaining reduced size and increased performance, particularly for high-frequency signal processing, due to complexity and cost associated with existing methods like TSV and flip chip processes.
Innovation Solution
A semiconductor package design featuring an offset stacking structure with a redistribution layer between semiconductor chips, allowing for electrical connection of non-aligned penetration vias or chip pads, which reduces the need for vertical connection structures and increases integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through-silicon via (TSV) process or flip chip process is used to stack memory chips, then device integration density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from traditional vertical alignment (2D plane alignment) to 3D offset stacking, where the second chip is positioned at a horizontal offset from the first chip. This dimensional change allows connection without requiring precise vertical alignment, thereby reducing manufacturing complexity while maintaining high integration density.
Solution Approach 2:
The patent introduces an interconnection layer as an intermediary component between the first and second chips. This interconnection layer includes pads and wiring portions that electrically connect the chips without requiring direct alignment between them, simplifying the manufacturing process while achieving high integration density.
2Volume of moving object
If chip size is reduced to meet portable device demands, then device size is decreased, but electrical characteristics such as reliability deteriorate
Solution Approach 1:
By offsetting the second chip horizontally from the first chip rather than aligning them vertically, the patent creates additional spatial separation. This allows the interconnection layer to provide longer, more reliable electrical connection paths even when chips are small, thereby maintaining electrical characteristics while reducing device size.
Solution Approach 2:
The interconnection layer serves as a mediator that provides robust electrical connections between small chips. The wiring portions in the interconnection layer can be designed with optimal lengths and paths, ensuring reliable signal transmission even when the chips themselves are miniaturized for portable devices.
Data Source
AI summary
A semiconductor package includes a lower semiconductor chip including a first circuit layer, an upper semiconductor chip disposed on the lower semiconductor chip and including a second circuit layer, and an interconnection layer disposed between the lower semiconductor chip and the upper semiconductor chip, the interconnection layer including a plurality of pads, including at least a first pad offset from the lower semiconductor chip or the upper semiconductor chip, and a wiring portion horizontally extended and connecting the first pad of the plurality of pads to a second pad of the plurality of pads disposed between the lower semiconductor chip and the upper semiconductor chip, wherein the wiring portion of the interconnection layer electrically connects the first circuit layer to the second circuit layer.