Offset-Stacked Semiconductor Package for Compact Thermal Routing
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving miniaturization, weight reduction, and cost-effective manufacturing while maintaining effective thermal management and electrical connectivity between stacked semiconductor chips.
Innovation Solution
A semiconductor package design featuring a rewiring structure with stacked chips offset in a horizontal direction, utilizing conductive pillars and seed layers for electrical connections, and a molding member for thermal management, along with adhesive layers for chip fixation, enabling efficient electrical pathways and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are sequentially attached on a package substrate in a cascade structure, then electrical connectivity between chips is achieved, but the package size increases and thermal management becomes more difficult
Solution Approach 1:
The patent transitions from a planar cascade structure to a three-dimensional stacked structure. Multiple semiconductor chips are arranged vertically in layers (first layer, second layer, third layer) and connected through conductive pillars that extend in the vertical direction. This dimensional change allows electrical connectivity to be achieved while reducing the horizontal package footprint area.
2Reliability
If semiconductor chips are sequentially attached on a package substrate in a cascade structure, then electrical connectivity between chips is achieved, but thermal dissipation becomes less efficient
Solution Approach 1:
The vertical stacking arrangement distributes heat-generating chips across multiple elevation levels rather than concentrating them in a single plane. This three-dimensional configuration increases the surface area available for thermal dissipation and allows heat to be conducted through conductive pillars to lower layers, improving overall thermal management efficiency.
3Reliability
If a plurality of conductive pillars are used for electrical connection between stacked chips, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The electrical connection system is segmented into discrete conductive pillars that are individually formed between adjacent chip layers. Each conductive pillar serves as an independent connection element, allowing for modular manufacturing where pillars can be formed, insulated with seed layers, and connected to specific chip regions in a systematic, repeatable process across multiple layers.
4Area of stationary object
If chips are offset stacked in a horizontal direction, then space utilization is improved, but alignment precision requirements increase
Solution Approach 1:
A seed layer is introduced as an intermediary element between the conductive pillars and the chip regions. This seed layer provides a transition zone that facilitates precise alignment and connection between the offset-stacked chips and the conductive pillars, reducing the direct alignment precision requirements between chips while maintaining reliable electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design simplifies manufacturing processes and enhances thermal characteristics by providing improved electrical connectivity and thermal management in a compact, cost-effective semiconductor package.
Implementation Method 1
a first adhesive layer on an upper surface of the first chip, a second adhesive layer on an upper surface of the second chip
Implementation Method 2
a first conductive pillar on the rewiring structure and spaced apart from the first metal layer in a first horizontal direction, a second chip on an upper surface of the first seed layer, and offset stacked from the first chip in the first horizontal direction, wherein the first conductive pillar overlaps the second chip in a vertical direction
Implementation Method 3
a first seed layer on an upper surface of the first adhesive layer, a second seed layer on an upper surface of the second adhesive layer
Data Source
AI summary
A semiconductor package includes a rewiring structure, a first chip on the rewiring structure, a first adhesive layer on an upper surface of the first chip, a first seed layer on an upper surface of the first adhesive layer, a first metal layer on a side surface of the first chip, a first conductive pillar on the rewiring structure and spaced apart from the first metal layer in a first horizontal direction, a second chip on an upper surface of the first seed layer, and offset stacked from the first chip in the first horizontal direction, and a second adhesive layer on an upper surface of the second chip, wherein the first conductive pillar overlaps the second chip in a vertical direction, and a portion of the first seed layer is disposed between the first conductive pillar and the second chip.