Offset-Stacked Semiconductor Packages for Heat and Width Limits

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Solution Overview

Problem

Current semiconductor packages face challenges in achieving high density and small form factor while maintaining high performance, particularly in mobile devices, due to limitations in stacking multiple semiconductor dies effectively and efficiently dissipating heat.

Innovation Solution

The solution involves forming a heat dissipation layer on a carrier, sequentially offset stacking semiconductor dies, creating vertical connectors, and encapsulating them with an encapsulant layer, along with forming redistribution layers connected to the vertical connectors, which allows for efficient heat dissipation and reduced package width.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple semiconductor dies are stacked to increase density, then the integration capacity and performance are improved, but the heat dissipation becomes more difficult and the package width increases

Engineering Contradiction:
Improveintegration capacityVSAvoidheat dissipation
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent transitions from planar packaging to three-dimensional stacking, arranging semiconductor dies vertically in multiple layers. This dimensional change allows multiple dies to be integrated within a compact footprint while maintaining accessibility to each die through side connections, thereby increasing integration capacity without proportionally increasing package width or heat dissipation challenges.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where semiconductor dies are stacked one inside another in a vertical arrangement. Each die is positioned within the vertical space occupied by the package structure, with connection terminals extending to the sides for external connectivity. This nesting approach maximizes the use of vertical space to accommodate multiple dies without significantly increasing the horizontal package dimensions.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Quantity of substance

If multiple semiconductor dies are stacked to increase density, then the integration capacity is improved, but the package width increases

Engineering Contradiction:
Improveintegration capacityVSAvoidpackage width
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from planar packaging to three-dimensional stacking, arranging semiconductor dies vertically in multiple layers. This dimensional change allows multiple dies to be integrated within a compact footprint, with connection terminals extending to the sides for external connectivity, thereby increasing integration capacity without proportionally increasing package width.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where semiconductor dies are stacked one inside another in a vertical arrangement. Each die is positioned within the vertical space occupied by the package structure, with connection terminals extending to the sides for external connectivity. This nesting approach maximizes the use of vertical space to accommodate multiple dies without significantly increasing the horizontal package dimensions.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Ease of manufacture

If conventional packaging structures are used, then the manufacturing process is simple, but the heat dissipation efficiency is poor

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidheat dissipation efficiency
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent transitions from planar packaging to three-dimensional stacking, arranging semiconductor dies vertically in multiple layers. This dimensional change allows multiple dies to be integrated within a compact footprint, with connection terminals extending to the sides for external connectivity, thereby increasing integration capacity without proportionally increasing package width.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where semiconductor dies are stacked one inside another in a vertical arrangement. Each die is positioned within the vertical space occupied by the package structure, with connection terminals extending to the sides for external connectivity. This nesting approach maximizes the use of vertical space to accommodate multiple dies without significantly increasing the horizontal package dimensions.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the creation of high-density, high-performance semiconductor packages with reduced size, improved heat dissipation, and enhanced connectivity, making them suitable for mobile devices and other applications.

Implementation Method 1

forming a heat dissipation layer on a carrier

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

forming an encapsulant layer connected to the heat dissipation layer and encapsulating the vertical connectors and the semiconductor dies

Methodology Applied
Scientific EffectPhysical containment: Physical Containment

Data Source

PatentUS20240234379A1Stack packages and methods of manufacturing the same
Publication Date: 2024.07.11 SK HYNIX INC
  • US20240234379A1 patent drawing
  • US20240234379A1 patent drawing
  • US20240234379A1 patent drawing

AI summary

A stack package, and a method of manufacturing the same, includes a heat dissipation layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the heat dissipation layer. Vertical connectors connected to the semiconductor dies are formed. An encapsulant layer coupled to the heat dissipation layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the encapsulant layer.