Offset Stacked Semiconductor Packages With Redistribution Pads
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Solution Overview
Problem
Highly integrated semiconductor chips are difficult to achieve due to technological limitations and increased costs, making it challenging to process high-volume data effectively within a single package.
Innovation Solution
A semiconductor package design that includes multiple semiconductor chips stacked in offset directions with redistribution pads and lines to facilitate electrical connections, reducing the complexity and length of bonding wires and preventing loop failures or short-circuits, while allowing for efficient data processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked in a single package to process high-volume data, then data processing capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the semiconductor package into multiple independent chips (first semiconductor chip, second semiconductor chip, third semiconductor chip) stacked vertically on the substrate. Each chip can be manufactured separately using standard processes, then assembled into the multi-chip package. This segmentation allows high data processing capability through parallel operation while managing complexity through modular design and standardized interconnection structures.
2Reliability
If traditional bonding wire connections are used between stacked chips, then electrical connections are established, but loop failures and short-circuits occur increasing reliability issues
Solution Approach 1:
The patent transitions from planar bonding wire connections to vertical interchip connections through redistribution pads and interchip connection structures. The first chip connects to the substrate via first redistribution pads, the second chip connects to the first chip via second redistribution pads, and the third chip connects to the second chip via third redistribution pads. This vertical stacking in the Z-dimension eliminates bonding wire loops and reduces short-circuit risks while improving connection reliability.
3Ease of manufacture
If chip size and electrode pad positions are fixed by manufacturing processes, then manufacturing is simplified, but flexible electrical connection and signal routing become difficult
Solution Approach 1:
The patent incorporates redistribution pads (first redistribution pads on the first chip, second redistribution pads on the second chip, third redistribution pads on the third chip) during chip manufacturing. These pads are pre-positioned and connected to internal circuit nodes before chip assembly. This preliminary action allows flexible signal routing and electrical connections in the final package while maintaining standard, simple chip manufacturing processes for each individual chip.
Data Source
AI summary
A plurality of semiconductor chips may be stacked on the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.