Nanostructure Transistors With Offset Superlattices for Dopant Blocking
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Solution Overview
Problem
Existing semiconductor devices face limitations in achieving enhanced charge carrier mobility and performance due to challenges in material defects, impurity scattering, and interface quality.
Innovation Solution
The method involves forming a semiconductor device with a superlattice structure that includes alternating layers of semiconductor materials, with non-semiconductor monolayers constrained within the crystal lattice of adjacent semiconductor portions, to reduce impurity scattering and improve interface quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor structures are used, then manufacturing is simpler, but charge carrier mobility is limited due to impurity scattering and interface defects
Solution Approach 1:
The semiconductor structure is segmented into multiple alternating layers of different materials (e.g., Si/SiGe superlattice) with distinct functions. Each layer is thin and contributes to reducing impurity scattering while maintaining crystal structure integrity, thereby improving charge carrier mobility without excessive complexity
Solution Approach 2:
Composite semiconductor materials are used in the superlattice structure, combining different semiconductor compounds (such as silicon and silicon-germanium) in alternating layers. This composite approach enables tailored band structures and reduced impurity scattering, enhancing charge carrier mobility while managing structural complexity
2Reliability
If dopant blocking structures are added to reduce impurity scattering, then charge carrier mobility improves, but manufacturing complexity increases
Solution Approach 1:
Dopant blocking structures are formed in advance during the epitaxial growth process, before final device fabrication steps. This preliminary action prevents impurity scattering from the outset, improving charge carrier mobility while integrating the blocking function into the existing manufacturing flow with minimal additional complexity
Solution Approach 2:
The dopant blocking structures act as intermediary elements between the source/drain regions and the channel, mediating the interaction by preventing dopant diffusion into the channel while maintaining electrical connectivity. This intermediary approach reduces impurity scattering without requiring complete isolation, balancing mobility improvement with manufacturing ease
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility by reducing charged impurity concentration and improving interface quality, leading to higher performance in semiconductor devices.
Implementation Method 1
The method involves forming a semiconductor device with a superlattice structure that includes alternating layers of semiconductor materials, with non-semiconductor monolayers constrained within the crystal lattice of adjacent semiconductor portions, to reduce impurity scattering and improve interface quality
Data Source
AI summary
A method for making semiconductor device may include forming spaced apart gate stacks on a substrate defining respective trenches therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, forming respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and forming respective dopant blocking superlattices adjacent lateral ends of the nanostructures and offset outwardly from adjacent surfaces of the insulating regions. Each dopant blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.