Offset Thin-Film Transistor Layout to Eliminate Overlap Capacitance
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Solution Overview
Problem
In thin film transistor designs, the overlap between the source and drain regions and the gate electrode leads to overlap capacitance, which reduces the switching speed of the transistor due to parasitic capacitance.
Innovation Solution
Embedding the bottom gate metal inside etch stop vias and positioning it in direct contact with a metal layer underneath prevents the source and drain regions from overlapping with the gate electrode, eliminating overlap capacitance and allowing the transistor to operate at a higher speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the source and drain regions overlap with the gate electrode, then the transistor structure is simpler, but overlap capacitance increases causing circuit delay
Solution Approach 1:
The patent introduces offset source and drain structures that are laterally displaced from the gate electrode in the planar dimension. This dimensional offset eliminates the vertical overlap between source/drain regions and gate electrode, thereby removing overlap capacitance while maintaining a relatively simple planar transistor structure.
2Ease of manufacture
If the source and drain regions overlap with the gate electrode, then the manufacturing process is easier, but switching speed decreases due to parasitic capacitance
Solution Approach 1:
The patent employs preliminary patterning steps where mandrels are formed first, followed by deposition of offset source and drain structures. This preliminary action establishes the lateral offset geometry before final electrode formation, enabling elimination of overlap capacitance while maintaining manufacturability through standard semiconductor fabrication processes.
Data Source
AI summary
A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.