Offset Transistor Column Layout for High-Density 2T0C DRAM
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Solution Overview
Problem
Current dynamic random access memory (DRAM) technologies face challenges in miniaturization due to high power consumption and complex manufacturing processes, particularly in 1T1C DRAM, and low integration in 2T0C DRAM due to perpendicular transistor arrangements.
Innovation Solution
A semiconductor structure with alternately arranged first and second transistor columns, where the transistors have the same length direction and offset centers, allowing for closer arrangement and eliminating the need for capacitors, thus simplifying the process and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 1T1C DRAM structure is used, then data storage capability is provided, but power consumption increases due to destructive reading requiring rewriting
Solution Approach 1:
The patent extracts and removes the capacitor component from the 1T1C DRAM structure, transitioning to a 2T0C architecture where data is stored in the transistor state itself rather than in a separate capacitor, thereby eliminating the need for destructive reading and subsequent rewriting operations
Solution Approach 2:
The transistor structure is designed to maintain its own state without requiring external capacitor support, where the transistor's conductance state directly represents stored data, enabling non-destructive read operations and self-sustaining data storage
2Reliability
If 1T1C DRAM structure is used, then data storage is achieved, but device dimension cannot be miniaturized due to high occupied volume of capacitor
Solution Approach 1:
By removing the capacitor component entirely, the patent eliminates the volume occupied by the capacitor and its associated structures, enabling significant miniaturization of the overall device footprint while maintaining data storage functionality through the transistor state
Solution Approach 2:
The patent merges the data storage function with the transistor structure itself, where the transistor's channel region serves as the storage medium, eliminating the need for separate capacitor structures and enabling tighter integration and smaller dimensions
3Productivity
If 2T0C DRAM structure is used, then integration density can be increased, but manufacturing complexity remains high
Solution Approach 1:
The patent segments the transistor structure into distinct functional regions (channel, source, drain) with specific material compositions, allowing each region to be optimized independently while simplifying the overall manufacturing process through controlled material deposition and patterning
Solution Approach 2:
The patent utilizes parameter changes in oxide semiconductor materials (such as stoichiometry and crystal structure) to achieve the desired electrical characteristics, enabling precise control of transistor performance without requiring complex manufacturing steps
4Ease of manufacture
If conventional transistor materials are used, then manufacturing is simpler, but carrier mobility is low and leakage current is high
Solution Approach 1:
The patent employs composite oxide semiconductor materials (such as In-Ga-Zn-O systems) that combine the advantages of different oxides to achieve high carrier mobility and low leakage current, with the specific composition optimized for both performance and manufacturability
Solution Approach 2:
The patent optimizes the stoichiometric parameters of the oxide semiconductor material (ratios of In, Ga, Zn, and O) to achieve the desired electrical characteristics, enabling precise control of carrier mobility and leakage current through compositional adjustment
Data Source
AI summary
A semiconductor structure includes a substrate, first transistor columns and second transistor columns on the substrate. The first transistor columns and the second transistor columns are alternately arranged. A first transistor column includes a plurality of first transistors arranged in a first direction. A second transistor column includes a plurality of second transistors arranged in the first directions. The plurality of first transistors in the first transistor column are electrically connected to the plurality of second transistors in the second transistor column in one-to-one correspondence. A length direction of the first transistor is the same as a length direction of the second transistor. A center of the first transistor is offset from a center of the second transistor in the first direction.