Offset Through-Silicon Via Area for Semiconductor Substrate Crack Prevention
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Solution Overview
Problem
The collective formation of through-silicon vias in a specific area of a semiconductor chip can lead to reduced strength, making the substrate susceptible to cracking under stress, such as thermal stress, due to differences in linear expansion coefficients between the substrate, wiring board, and sealing resin.
Innovation Solution
A semiconductor device configuration where the through-silicon via area is arranged with long sides parallel to the semiconductor chip's long sides, and its center is offset from the chip's center, combined with a sealing resin and connection terminals layout that distributes stress and prevents warpage, enhancing mechanical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias are collectively formed in a specific area of the semiconductor chip substrate, then electrical connectivity is improved, but the substrate strength is reduced making it susceptible to cracking
Solution Approach 1:
The patent applies asymmetry by positioning the through-silicon via area such that its center is offset from the center of the semiconductor chip in the column direction. This asymmetric arrangement prevents the via area from being located at the position of maximum stress concentration, thereby resolving the contradiction between achieving good electrical connectivity through collective via formation and maintaining substrate strength to prevent cracking.
2Ease of manufacture
If the through-silicon via area is positioned at the center of the semiconductor chip, then manufacturing alignment is simplified, but stress concentration increases leading to substrate cracking
Solution Approach 1:
The patent deliberately introduces asymmetry by offsetting the through-silicon via area from the chip center in the column direction. This design choice prioritizes stress distribution and crack prevention over manufacturing alignment simplicity, accepting that slightly more complex alignment procedures are necessary to achieve reliable crack-free substrates.
Solution Approach 2:
The patent applies local quality by specifically positioning the via area in a region with lower stress concentration (offset from center in column direction) while maintaining other areas of the chip with standard properties. This localized adjustment optimizes the vulnerable via region without affecting other chip functions.
3Reliability
If the through-silicon via area is offset from the chip center, then stress distribution is improved preventing cracks, but manufacturing alignment becomes more difficult
Solution Approach 1:
The patent accepts the increased alignment complexity as a necessary trade-off for achieving reliable crack prevention. The asymmetric positioning of the via area is implemented with specific offset distances (0.5mm to 2.0mm) that can be incorporated into manufacturing specifications, managing the complexity through standardized design rules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents cracking of the semiconductor chip substrate by distributing stress and maintaining mechanical reliability, even under thermal stress conditions.
Implementation Method 1
the second semiconductor chip is electrically coupled to first through-silicon vias of the first semiconductor chip
Implementation Method 2
differences in linear expansion coefficients between the substrate, wiring board, and sealing resin
Data Source
AI summary
This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.