Electronic Device Packaging With Offset-Verified Multilayer Traces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In large-area packaging processes like wafer-level and panel-level packaging, die-bond and molding processes lead to varying offset conditions among dies, compromising electrical reliability, and increasing the annular ring size to address this issue occupies more circuit design space, reducing product competitiveness.
Innovation Solution
A manufacturing method that involves providing first and second electronic units on a carrier, surrounding them with an insulating layer, thinning it to expose portions, performing offset verification, and creating a circuit structure with conductor layers to connect traces, allowing for better electrical reliability without altering the annular ring design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the annular ring is increased to cope with die offset, then electrical reliability is improved, but circuit design space is reduced
Solution Approach 1:
The patent transitions from a two-dimensional planar annular ring structure to a three-dimensional multi-layer conductor structure. By stacking conductor layers vertically and using via holes for inter-layer connections, the circuit achieves offset compensation in the vertical dimension rather than requiring horizontal space expansion, thus preserving circuit design space while improving electrical reliability
Solution Approach 2:
The patent implements nested conductor layers where multiple conductor layers are stacked within the same horizontal footprint. The first conductor layer, second conductor layer, and third conductor layer are nested vertically, with via holes providing electrical connections between them. This nested arrangement allows offset compensation without increasing the horizontal area, resolving the contradiction between reliability and space utilization
2Manufacturing precision
If the annular ring design is changed to improve electrical reliability, then connection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the conductor path into multiple discrete layers (first conductor layer, second conductor layer, third conductor layer) connected by via holes. Each layer can be independently optimized and manufactured, allowing precise control over connection accuracy while managing complexity through modular construction. The segmentation enables offset verification and compensation at each layer interface
Solution Approach 2:
The patent performs offset verification on electronic units before final circuit structure configuration. By calculating and confirming the offset positions in advance, the circuit structure can be precisely designed to accommodate the actual die positions, improving connection accuracy without requiring complex post-adjustment mechanisms
Data Source
AI summary
A manufacturing method of the electronic device includes the following steps. A first electronic unit and a second electronic unit are provided on a carrier. An insulating layer is provided to surround the first electronic unit and the second electronic unit. The insulating layer is grinded to expose at least a portion of the first electronic unit and at least a portion of the second electronic unit. An offset verification is performed on at least one of the first electronic unit and the second electronic unit to obtain an offset result. A circuit structure is provided on the insulating layer according to the offset result. The circuit structure includes a first conductor layer and a second conductor layer. The first conductor layer includes a first trace and a second trace, and the first trace and the second trace are electrically connected via the second conductor layer.