Offset Conductive Via Layout for Stress-Resistant Electronic Packages

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Solution Overview

Problem

Conventional semiconductor packages face issues with conductive vias tilting or breaking due to direct stress transmission through conductive bumps, leading to electrical failure and reduced reliability.

Innovation Solution

The design of conductive vias in the electronic package features a central axis offset from the central axis of conductive members, with a deviation of ¼ to ½ of the member's width, preventing direct stress transmission and maintaining package reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive vias are disposed directly on conductive bumps, then electrical connection is achieved, but stress is transmitted directly to conductive vias causing tilting or breakage

Engineering Contradiction:

Improvereliability of semiconductor packageVSAvoidstrength of conductive vias

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent applies asymmetry by deliberately offsetting the central axis of conductive vias from the central axis of conductive bumps. This asymmetric positioning ensures that conductive vias are not directly above conductive bumps, preventing direct stress transmission while maintaining electrical connection functionality.

Inventive Principle:

Principle #4Asymmetry

Solution Approach 2:

The patent introduces an intermediary approach by positioning conductive vias at offset locations relative to conductive bumps. This intermediary positioning acts as a buffer zone that prevents direct mechanical coupling between the bump structure and via structure, thereby reducing stress transmission while maintaining electrical connectivity.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If conductive vias are offset from conductive members, then stress transmission is prevented, but manufacturing alignment complexity increases

Engineering Contradiction:

Improvereliability of semiconductor packageVSAvoidalignment precision of conductive vias and members

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent specifies a particular offset parameter range (1/4 to 1/2 of the width of conductive members) to optimize the balance between stress prevention and manufacturing feasibility. This parameter change transforms the design from a direct alignment approach to a controlled offset approach with defined tolerances.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250279347A1Electronic package and manufacturing method thereof

Publication Date: 2025.09.04 SILICONWARE PRECISION IND CO LTD

AI summary

Provided is an electronic package including a carrier structure and a packaging module disposed on the carrier structure by a plurality of conductive members. The packaging module includes a plurality of circuit layers and a plurality of conductive vias, wherein the plurality of conductive vias are electrically connected to two of the circuit layers respectively, and a central axis of each of the conductive vias is deviated from a central axis of each of the conductive members. By the implementation of the present disclosure, the stresses or the external forces exerted on the conductive members can be prevented from being directly transferred to the conductive vias which would otherwise cause the conductive vias to tilt or even the electronic package to fail, such that the reliability of the electronic package can be enhanced.