Offset Via Structure for Self-Aligned Partially Filled Trenches
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Solution Overview
Problem
The challenge in forming integrated circuits is aligning small vertical metal lines (vias) to connect different layers of horizontal metal lines without misalignment, which can cause vias to be too close to neighboring lines, leading to increased complexity and reduced contact efficiency in semiconductor manufacturing.
Innovation Solution
The method involves forming metal lines as partially filled trenches, using a buffer layer and sacrificial material to create a via that is self-aligned and offset, ensuring proper contact with the intended metal line while maintaining a safe distance from neighboring lines, utilizing techniques like photolithography, etching, and chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via alignment methods are used, then via formation is simpler, but misalignment occurs causing vias to be too close to neighboring metal lines
Solution Approach 1:
The patent applies preliminary action by forming a buffer layer and sacrificial material structure before via formation. The buffer layer is deposited and patterned first, followed by sacrificial material filling, creating a pre-positioned alignment structure that guides subsequent via formation and ensures precise positioning relative to metal lines.
Solution Approach 2:
The patent uses an intermediary approach by introducing a buffer layer and sacrificial material as intermediate structures between the metal lines and the via. These intermediary layers facilitate precise alignment by providing a controlled interface that mediates the positioning relationship between the via and underlying metal lines.
2Reliability
If additional spacing is maintained between metal lines to avoid misalignment issues, then manufacturing is simpler, but functional density decreases
Solution Approach 1:
The patent applies local quality by creating a localized buffer zone using the buffer layer and sacrificial material specifically at via locations. This localized structure provides enhanced alignment control and spacing management only where needed (at via-metalline interfaces) rather than requiring uniform spacing across the entire chip, thus improving contact reliability without sacrificing overall area utilization.
Solution Approach 2:
The patent transitions to another dimension by adding vertical buffer layers and sacrificial material structures between the horizontal metal lines and via openings. This vertical dimensionality change creates additional spacing and alignment control in the Z-direction, allowing closer horizontal spacing of metal lines while maintaining reliable via contact through the vertically-extending buffer structure.
3Productivity
If metal lines are spaced closer together to increase functional density, then chip area utilization improves, but misalignment risk increases
Solution Approach 1:
The patent uses preliminary action by pre-forming the buffer layer and sacrificial material structure before via formation. This preliminary structure establishes precise spacing and alignment references that guide subsequent via drilling or etching, ensuring accurate via positioning even when metal lines are closely spaced, thus maintaining manufacturing precision while enabling higher functional density.
Solution Approach 2:
The patent introduces intermediary buffer layers and sacrificial material structures that act as mediators between closely-spaced metal lines and vias. These intermediary elements provide controlled spacing and alignment references that enable precise via positioning relative to neighboring metal lines, allowing closer metal line spacing without compromising alignment accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more efficient alignment and reduced contact resistance between metal lines, enabling closer spacing of metal lines in integrated circuits while minimizing misalignment issues, thereby improving manufacturing efficiency and reducing the need for additional spacing between lines.
Implementation Method 1
depositing a buffer layer on the first interlayer dielectric layer
Implementation Method 2
patterning the buffer layer to form a hole within the buffer layer to expose the sacrificial material, and removing the sacrificial material
Implementation Method 3
filling the hole and the trench with a metal material to form a via
Data Source
AI summary
An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.