Offset Via Arrangements for Stacked Semiconductor Stress Relief

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Solution Overview

Problem

Semiconductor devices face challenges in achieving structural stability and reliability due to mechanical stress caused by thermal expansion, particularly in stacked chip configurations where vias and connection regions overlap, leading to potential electrical and physical deterioration.

Innovation Solution

The semiconductor device incorporates a unique I/O interconnection structure with laterally spaced apart vias, connection regions, and through vias, which reduces mechanical stress by distributing it across a larger volume, preventing overlap and enhancing structural stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vias and connection regions are overlapped in stacked chip configurations, then electrical interconnection is achieved, but mechanical stress concentrates leading to structural instability and reliability deterioration

Engineering Contradiction:

Improvestructural stabilityVSAvoidmechanical stress

Core Design Contradiction:

ReliabilityVSStress or pressure

Solution Approach 1:

The via structure is segmented into two distinct components: regular vias for electrical interconnection between metal layers, and offset through vias for mechanical stress relief. This segmentation allows each via type to perform its specialized function without compromising the other, resolving the contradiction between electrical connectivity and stress distribution.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Offset through vias act as intermediary elements that do not directly participate in electrical signal transmission but serve as stress distribution mediators. These vias are positioned to overlap with connection regions, providing a pathway for stress relief while maintaining electrical integrity through the connection layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If vias are densely packed for high interconnection density, then electrical connectivity is improved, but mechanical stress concentration increases causing potential deterioration

Engineering Contradiction:

Improveinterconnection densityVSAvoidstructural reliability

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

Different regions of the via structure are assigned different qualities and functions: regular vias in non-overlapping regions provide high-density electrical interconnection, while offset through vias in overlapping regions provide stress relief. This local differentiation allows the structure to simultaneously achieve high interconnection density and structural reliability.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS9780136B2Composite wafer semiconductor devices using offset via arrangements and methods of fabricating the same

Publication Date: 2017.10.03 SAMSUNG ELECTRONICS CO LTD

AI summary

A device includes a first integrated circuit substrate including a plurality of first metal layers interconnected by first vias and a second integrated circuit substrate on the first integrated circuit substrate and including second metal layers interconnected by second vias. An insulation layer is disposed between the first and second substrates and a connection region is disposed in the insulation layer and electrically connects a first one of the first metal layers to a first one of the second metal layers. The device further includes a bonding pad on the second substrate and a through via extending from the bonding pad and into the second to contact a second one of the second metal layers. The through via is positioned so as to not overlap at least one of the first vias, the second vias and the connection region. Methods of fabricating such device are also described.