Offset Via Stacking Structures for Semiconductor Packaging Stress Relief
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing density of I/O pads in semiconductor dies leads to packaging challenges, affecting yield due to high stress from components with high Coefficient of Thermal Expansion (CTE) values.
Innovation Solution
The formation of eccentric bonding structures with offset conductive pads and vias, reducing stress by misaligning the centers of conductive bumps, pads, and vias, and using flexible redistribution lines to absorb stress without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If I/O pad density is increased to integrate more functions into smaller semiconductor dies, then functional integration is improved, but packaging difficulty increases and yield decreases due to high stress from components with high CTE values
Solution Approach 1:
The patent applies asymmetry by intentionally misaligning the centers of conductive bumps, pads, and vias to create eccentric bonding structures. This asymmetric configuration generates stress relief that prevents delamination and trace breaking, thereby improving packaging reliability while maintaining high I/O pad density
Solution Approach 2:
The patent changes the geometric parameters of the bonding structures by offsetting the centers of conductive bumps, pads, and vias from each other. This parameter modification creates eccentric structures that reduce thermal expansion stress, allowing high I/O pad density to be achieved without compromising packaging yield
2Ease of manufacture
If conventional aligned bonding structures are used, then manufacturing simplicity is maintained, but stress from high CTE components causes delamination and trace breaking
Solution Approach 1:
The patent transitions from symmetric aligned structures to asymmetric eccentric structures by offsetting the centers of conductive bumps, pads, and vias. This asymmetric design maintains manufacturing feasibility while dramatically improving bonding reliability by reducing stress-induced failures
3Reliability
If stress relief structures are implemented to prevent delamination, then bonding reliability is improved, but chip area increases
Solution Approach 1:
The patent applies local quality by implementing stress relief through eccentric offsetting specifically at the bonding interfaces (conductive bumps, pads, and vias) rather than throughout the entire chip structure. This localized approach provides effective stress relief and improved reliability without increasing overall chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces stress in semiconductor packaging, preventing delamination and trace breaking while maintaining manufacturing efficiency and chip area utilization.
Implementation Method 1
high stress from components with high Coefficient of Thermal Expansion (CTE) values
Data Source
AI summary
A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.