Isolated Ohmic Trenches in HVSOI Substrates
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Solution Overview
Problem
In the fabrication of High Voltage Silicon on Insulator (HVSOI) semiconductor structures, there is a need for a thick Si layer and ohmic electrical contact to bulk silicon, along with isolated ohmic trenches to contact multiple regions, while ensuring device-to-device isolation, which is challenging due to the requirement for both shallow trench isolation and sufficient silicon thickness for CMOS well implants and LDMOS drift regions.
Innovation Solution
A method and structure that simultaneously form ohmic and isolation trenches in a silicon-on-insulator (SOI) substrate using self-alignment techniques, where insulating material is introduced to provide electrical insulation, and semiconductor material is used to create ohmic contact trenches, while dielectric material forms device isolation trenches, integrating the advantages of SOI and bulk CMOS technologies in a cost-effective manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If a thick Si layer is used in SOI substrate to maintain sufficient silicon for LDMOS drift region and CMOS well implants, then the silicon thickness requirement is met, but device-to-device isolation becomes difficult to achieve
Solution Approach 1:
The patent divides the isolation structure into two segments: shallow trench isolation (STI) regions that provide device-to-device isolation at the surface level, and deep isolation trenches that extend through the thick silicon layer to the handle wafer. This segmentation allows the thick silicon layer to be maintained for LDMOS drift region while still achieving adequate device isolation through the combination of STI and deep isolation trenches.
Solution Approach 2:
The patent implements a nested structure where shallow trench isolation regions are positioned within or adjacent to deep isolation trenches. The STI regions are filled with dielectric material and positioned to provide surface-level isolation, while the deep isolation trenches extend beneath them to provide substrate-level isolation. This nesting allows both isolation mechanisms to work together within the thick silicon layer structure.
2Adaptability or versatility
If multiple ohmic trenches are formed to contact multiple regions in bulk silicon, then electrical contact to multiple regions is achieved, but process complexity increases
Solution Approach 1:
The patent creates deep isolation trenches that serve multiple functions: they provide device-to-device isolation, enable electrical contact to the handle wafer through ohmic contact regions, and allow for selective doping of different regions. By forming these trenches to extend through the thick silicon layer to the handle wafer, the structure can contact multiple regions and provide both isolation and electrical connection functions.
Solution Approach 2:
The patent combines the isolation function and ohmic contact function into a single deep trench structure. Rather than forming separate isolation trenches and separate ohmic contact trenches, the deep isolation trenches are formed to extend through the silicon layer to the handle wafer, and ohmic contact regions are created within these same trenches. This merging reduces the number of separate formation steps required.
3Reliability
If shallow trench isolation is implemented to provide device isolation, then isolation is achieved, but sufficient silicon thickness for LDMOS drift region cannot be maintained
Solution Approach 1:
The patent segments the isolation structure into shallow trench isolation regions that provide device-to-device isolation at the surface, and deep isolation trenches that extend beneath the STI regions to the handle wafer. This segmentation allows the thick silicon layer to be maintained for LDMOS drift region while the STI regions provide the necessary device isolation at the active device level.
Solution Approach 2:
The patent adds the vertical dimension to the isolation structure by forming deep isolation trenches that extend through the thick silicon layer to the handle wafer, beneath the shallow trench isolation regions. This vertical extension allows device isolation to be achieved without reducing the overall silicon layer thickness, as the deep trenches provide isolation pathways that do not interfere with the LDMOS drift region formation in the vertical dimension.
Data Source
AI summary
A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.