Oldest Operation TLB Buffer for Load Queue Optimization

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Solution Overview

Problem

Modern data processor architectures face challenges in efficiently executing speculative memory operations and non-cacheable instructions due to issues like live-lock states and coherency problems, which require significant additional flip-flops for TLB information storage, leading to power consumption and timing pressures.

Innovation Solution

A method and apparatus that utilize a translation look-aside buffer (TLB) content addressable memory (CAM) and an oldest operation storage buffer, coupled with an output multiplexor, to determine and execute the oldest load operation, reducing the need for physical address flip-flops and ensuring reliable execution by storing translations in the oldest operation TLB buffer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If special flip-flops are added to load queues to hold TLB information, then reliability of load operation execution is improved, but device complexity increases

Engineering Contradiction:
Improvereliability of load operation executionVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the TLB information storage function with the existing load queue structure by using the oldest load queue entry to hold TLB data. Instead of adding separate flip-flops, the solution combines address and memory type information into the oldest load queue entry, thereby improving reliability without increasing device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The oldest load queue entry is given multiple functions: it continues to track the oldest load operation for ordering purposes while simultaneously storing TLB information (physical address and memory type). This multi-functionality eliminates the need for dedicated flip-flops while ensuring reliable execution of non-cacheable and cacheable instructions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If extra flip-flops are used to store TLB information, then reliability is improved, but power consumption increases

Engineering Contradiction:
ImprovereliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

By merging TLB information storage into the existing load queue entry, the patent eliminates the need for additional flip-flops that would consume power. The oldest load queue entry already exists and is maintained for ordering purposes, so reusing it for TLB storage avoids the power cost of additional storage elements.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent recovers the use of the oldest load queue entry for dual purposes. Instead of discarding this entry after use, the system retains and repurposes it to store TLB information, thereby avoiding the need for new storage elements that would increase power consumption.

Inventive Principle:
Principle #34Discarding and recovering

3Reliability

If additional flip-flops are added for TLB information storage, then reliability is improved, but timing pressure increases

Engineering Contradiction:
ImprovereliabilityVSAvoidtiming pressure
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent combines TLB information storage with the existing load queue entry, eliminating the need for additional flip-flops that would introduce timing delays. By reusing the oldest load queue entry, the system avoids the timing overhead associated with writing to and reading from separate storage elements.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The oldest load queue entry serves itself by simultaneously maintaining load operation ordering information and storing TLB data. This self-service approach eliminates the need for additional storage elements and the associated timing delays, as the same structure performs multiple functions without requiring extra access cycles.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9286233B2Oldest operation translation look-aside buffer
Publication Date: 2016.03.15 ADVANCED MICRO DEVICES INC
  • US9286233B2 patent drawing
  • US9286233B2 patent drawing
  • US9286233B2 patent drawing

AI summary

A method is provided for dispatching a load operation to a processing device and determining that the operation is the oldest load operation. The method also includes executing the operation in response to determining the operation is the oldest load operation. Computer readable storage media for performing the method are also provided. An apparatus is provided that includes a translation look-aside buffer (TLB) content addressable memory (CAM), and includes an oldest operation storage buffer operationally coupled to the TLB CAM. The apparatus also includes an output multiplexor operationally coupled to the TLB CAM and to the oldest operation storage buffer. Computer readable storage media for adapting a fabrication facility to manufacture the apparatus are also provided.