OLED Array Substrate Layout for Low Cross-Talk and Anode Stability

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Solution Overview

Problem

Current OLED display technologies face challenges in maintaining display quality due to cross-talk between signal nodes and adjacent data lines, which affects the display's brightness and color accuracy, particularly at large viewing angles.

Innovation Solution

The array substrate incorporates an interference preventing block and a specific configuration of voltage supply lines and initialization connecting lines to reduce parasitic capacitance and cross-talk, enhancing light transmittance and preventing anode tilting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If signal lines are routed close to data lines to reduce device area, then area is reduced, but cross-talk between signal nodes and adjacent data lines increases

Engineering Contradiction:
Improvedevice areaVSAvoidcross-talk
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

An interference preventing block is introduced as an intermediary structure between the initialization connecting line and the data line. This block acts as a mediator that reduces parasitic capacitance and cross-talk while allowing the lines to remain in close proximity, thus resolving the contradiction between small area and low cross-talk.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The interference preventing block is placed locally at specific positions where cross-talk is most problematic, rather than uniformly across the entire device. This localized approach reduces cross-talk at critical points while maintaining overall device compactness.

Inventive Principle:
Principle #3Local quality

2Reliability

If voltage supply lines are positioned to improve electrical connection, then electrical performance is improved, but anode tilting occurs due to uneven electrical fields

Engineering Contradiction:
Improveelectrical connectionVSAvoidanode orientation
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The interference preventing block serves as a counterbalancing element that compensates for the uneven electrical field distribution caused by voltage supply lines. By positioning this block strategically, it counteracts the force causing anode tilting, thus maintaining both good electrical connection and proper anode orientation.

Inventive Principle:
Principle #8Anti-weight (Counterweight)

3Ease of operation

If initialization connecting lines are extended to ensure complete signal coverage, then signal coverage is improved, but parasitic capacitance with adjacent data lines increases

Engineering Contradiction:
Improvesignal coverageVSAvoidparasitic capacitance
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The interference preventing block is positioned between the initialization connecting line and the adjacent data line to act as a mediator. It reduces the parasitic capacitance coupling between these lines while still allowing the initialization signal to cover the required area, thus resolving the contradiction between signal coverage and parasitic capacitance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly reduces vertical cross-talk by at least 50%, improving display quality and minimizing color shift at large viewing angles.

Implementation Method 1

cross-talk between signal nodes and adjacent data lines

Methodology Applied
Scientific EffectParasitic capacitance: Parasitic Capacitance

Data Source

PatentUS11800759B2Array substrate and display apparatus
Publication Date: 2023.10.24 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US11800759B2 patent drawing
  • US11800759B2 patent drawing
  • US11800759B2 patent drawing

AI summary

An array substrate is provided. The array substrate includes a respective first anode electrically connected to a respective first light emitting element in a respective first subpixel; a respective second anode electrically connected to a respective second light emitting element in a respective second subpixel; a respective third anode electrically connected to a respective third light emitting element in a respective third subpixel; and a respective fourth anode electrically connected to a respective fourth light emitting element in a respective fourth subpixel. An orthographic projection of the respective third anode on a base substrate substantially covers an orthographic projection of the first initialization connecting line on the base substrate, and covers an orthographic projection of at least portion of the respective third voltage supply line on the base substrate.