OLED Array Substrate Layout for Pixel Node Cross-Talk Reduction
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Solution Overview
Problem
Existing OLED display technologies face issues with cross-talk between pixel nodes and adjacent data lines, affecting display quality.
Innovation Solution
The array substrate incorporates an interference preventing block and a node connecting line configuration that spaces the node connecting line from adjacent data lines, using arms to prevent cross-talk, with specific geometric relationships and overlapping structures to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the node connecting line is placed close to data lines for compact layout, then device complexity is reduced, but cross-talk interference increases
Solution Approach 1:
The patent introduces an interference preventing block as an intermediary structure positioned between the node connecting line and adjacent data lines. This block acts as a mediator that physically separates the conductive elements, preventing direct electromagnetic coupling while maintaining the compact layout. The interference preventing block serves as a barrier that blocks harmful electromagnetic fields from causing cross-talk between the node connecting line and data lines.
Solution Approach 2:
The patent segments the conductive structures by dividing the space between the node connecting line and data lines with the interference preventing block. This segmentation creates distinct electromagnetic zones, isolating the node connecting line from the data lines and preventing cross-talk. The segmentation approach allows the layout to remain compact while eliminating harmful electromagnetic interactions through spatial separation.
2Object-affected harmful factors
If the node connecting line is spaced apart from adjacent data lines, then cross-talk interference is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The interference preventing block serves as a mediator that establishes a fixed, controlled spacing between the node connecting line and data lines. By incorporating this intermediary structure, the patent transforms the spacing requirement from a precise dimensional control challenge into a structural design problem. The block's geometry defines the separation distance, making it easier to manufacture with standard precision tolerances while maintaining effective cross-talk prevention.
Solution Approach 2:
The interference preventing block acts as a sacrificial or temporary structure during the manufacturing process that simplifies precision requirements. Rather than requiring extremely precise spacing between conductive elements, the patent uses the block to establish robust, toleranced spacing. The block can be formed through standard lithography and etching processes, converting high-precision requirements into more manageable manufacturing steps.
3Use of energy by moving object
If voltage supply lines are positioned to cover large areas, then power distribution is improved, but parasitic capacitance with adjacent lines increases
Solution Approach 1:
The patent applies local quality by positioning the interference preventing block specifically at locations where parasitic capacitance would be problematic. Rather than uniformly spacing all conductive elements, the block is strategically placed only where voltage supply lines are in close proximity to data lines, providing localized protection against parasitic capacitance while maintaining overall power distribution efficiency.
Solution Approach 2:
The interference preventing block serves as an intermediary barrier between voltage supply lines and data lines, mediating the electromagnetic interaction. This block allows the voltage supply lines to extend over large areas for efficient power distribution while preventing excessive parasitic capacitance formation with adjacent data lines through physical separation and electromagnetic shielding.
Data Source
AI summary
An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by a first arm, and is spaced apart from a second adjacent data line by a second arm.