OLED Array Substrate Layout for Low-Capacitance Detection Lines
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Solution Overview
Problem
Existing OLED display panels face issues with high parasitic capacitance and reduced product yield due to overlapping detection lines and data lines, which affect signal transmission efficiency and are prone to static electricity-induced short circuits.
Innovation Solution
The array substrate design alternately shares detection line structures between adjacent rows of subpixels, reducing the number of detection lines and power supply lines, thereby minimizing line overlaps and parasitic capacitance, and enhances detection speed by distributing detection lines across multiple regions within each row.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detection lines are provided for each row of subpixels, then detection coverage is improved, but parasitic capacitance increases and product yield decreases
Solution Approach 1:
The patent merges the detection lines for adjacent rows by having a single detection line serve multiple subpixel rows. The detection line is extended to connect to switching transistors in multiple rows, allowing simultaneous or sequential detection of electrical characteristics across different rows. This consolidation reduces the total number of detection lines, thereby reducing parasitic capacitance and improving product yield while maintaining comprehensive detection coverage.
2Adaptability or versatility
If detection lines overlap with data lines, then routing flexibility is improved, but yield decreases due to parasitic capacitance
Solution Approach 1:
The patent resolves the routing conflict by utilizing the column dimension. Instead of allowing detection lines to overlap with data lines in the same row (horizontal dimension), the detection lines are routed through the column dimension by connecting to switching transistors that are selectively activated. This dimensional separation allows detection and data signaling to coexist without parasitic capacitance issues while maintaining routing flexibility.
3Object-affected harmful factors
If number of detection lines is reduced, then parasitic capacitance is reduced, but detection speed may decrease
Solution Approach 1:
The patent implements periodic action by sequentially activating switching transistors in different rows through column-scan signals. Although a single detection line serves multiple rows, the systematic sequential activation ensures that each row is detected in a regular periodic manner. This maintains detection speed by ensuring that no row is left undetected and that the detection process proceeds efficiently through all rows in a structured sequence.
Data Source
AI summary
An array substrate is provided. The array substrate includes a plurality of subpixels and a plurality of detection line structures. The plurality of subpixels are arranged in an array of a plurality of rows and a plurality of columns along a first direction and a second direction. Each of the plurality of detection line structures includes at least one first detection line extending along the first direction; adjacent (n)th row and (n+1)th row of subpixels in the array form a subpixel row group, one detection line structure is provided between the (n)th row and (n+1)th row of subpixels in each subpixel row group, and the detection line structure is configured to be connected to the (n)th row and (n+1)th row of subpixels and detect electrical characteristics of first transistors or light-emitting elements in the subpixels.