OLED Array Base Plate Layout for Lower IR Drop and Stable Pixels
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Solution Overview
Problem
Existing silicon-based OLED micro displays face challenges in achieving efficient pixel driving and signal stability due to issues like IR Drop and signal crosstalk, which affect the uniformity and stability of luminous brightness.
Innovation Solution
The array base plate design includes a substrate with sub-pixels containing pixel driving circuits and light emitting devices, featuring specific wiring and transistor configurations that enhance conductivity and reduce IR Drop, while overlapping projections of signal lines improve signal stability and layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wiring layouts are used in silicon-based OLED micro displays, then device complexity is reduced, but IR Drop occurs and conductivity of power signal lines deteriorates, affecting luminous brightness uniformity
Solution Approach 1:
The patent applies dimensionality change by having the first wiring extend in a direction substantially perpendicular to the gate of the third transistor, rather than parallel to it. This perpendicular arrangement optimizes the spatial distribution of current flow, reducing IR Drop effects and improving conductivity of the power signal line while maintaining compact layout.
Solution Approach 2:
The patent implements local quality optimization by specifically designing the first wiring's extension direction to be perpendicular to the transistor gate in the region where it connects to the first control signal line. This localized structural adjustment targets the critical area for power signal transmission, improving luminous brightness uniformity without increasing overall device complexity.
2Reliability
If signal lines are routed to avoid overlap, then signal crosstalk is reduced, but area occupied by wiring increases and layout efficiency decreases
Solution Approach 1:
The patent utilizes dimensional arrangement by configuring the first wiring to extend perpendicular to the transistor gate, allowing it to overlap with the gate structure in the planar view while maintaining proper electrical isolation through layering. This approach reduces the area occupied by wiring while preventing signal crosstalk through appropriate layer separation.
Solution Approach 2:
The patent applies nesting by allowing the first wiring to be positioned over the transistor gate structure, effectively utilizing the vertical space above existing components. This nested arrangement minimizes the horizontal area required for wiring while maintaining signal integrity through proper layer isolation.
3Loss of energy
If wiring is optimized for conductivity, then IR Drop is reduced, but device complexity increases due to specific wiring configurations
Solution Approach 1:
The patent achieves improved conductivity with minimal added complexity by simply changing the extension direction of the first wiring to be perpendicular to the transistor gate. This single directional change optimizes current flow paths and reduces IR Drop without requiring complex multi-layer routing or additional wiring structures.
Solution Approach 2:
The patent implements parameter change by modifying the orientation angle of the first wiring relative to the transistor gate from parallel to perpendicular. This parameter adjustment optimizes the electrical characteristics and reduces IR Drop while maintaining compatibility with existing manufacturing processes and device architecture.
Data Source
AI summary
An array base plate, wherein the array base plate comprises a substrate and a plurality of sub-pixels that are located on the substrate and arranged in array, and each of the sub-pixels comprises a pixel driving circuit and a light emitting device that are electrically connected. The pixel driving circuit comprises a drive module and a first control module, wherein the drive module is electrically connected to a first node, a second node and an anode of the light emitting device, wherein the drive module is configured for conducting a path between the second node and the anode under control of a voltage of the first node, and generating a current in the path to make the light emitting device emit light. The first control module is electrically connected to a first control signal line, a second power signal line and the anode of the light emitting device.