OLED Array Substrate Layout for High-PPI Low-Resistance Wiring
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Solution Overview
Problem
Existing OLED display technologies face challenges in optimizing the layout of conductive layers and signal lines, leading to restricted wiring space, high resistance, and increased risk of short circuits, which hinder the development of high pixel density displays.
Innovation Solution
The array substrate design includes a multi-layered structure with separate conductive layers for data, power, and sensing lines, along with a novel storage capacitor configuration, utilizing multiplexed electrodes and via holes to reduce resistance and short circuit risks, while allowing for higher pixel density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple conductive layers are used to increase pixel density, then the pixel per inch (PPI) increases, but the wiring resistance and IR drop increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional stacked conductive layers (first, second, and third conductive layers at different heights). This vertical dimensionality change allows signal lines to be routed through multiple layers, reducing the horizontal wiring length and thus reducing wiring resistance and IR drop while maintaining high pixel density.
Solution Approach 2:
The wiring is segmented across multiple conductive layers rather than using single-layer long traces. Each conductive layer handles specific routing segments, and via holes connect them vertically. This segmentation reduces the path length in each layer and distributes the electrical load, lowering overall resistance.
2Quantity of substance
If conductive layers are closely arranged to increase pixel density, then the PPI increases, but the probability of short circuits increases
Solution Approach 1:
By moving wiring routes to the vertical dimension with stacked conductive layers, the patent reduces horizontal proximity between signal lines. The via holes provide controlled vertical connections, spatially separating adjacent wiring paths and reducing capacitive coupling and short circuit risks while maintaining high pixel density.
Solution Approach 2:
Via holes serve as intermediary connection elements between conductive layers. These precisely controlled vertical conduits provide isolated connection points, mediating the electrical connection while maintaining spatial separation between horizontal wiring paths, thus reducing short circuit probability.
3Reliability
If wiring space is increased to reduce resistance, then the IR drop decreases, but the pixel density decreases
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension with multiple stacked conductive layers. This allows sufficient wiring space and longer effective cross-section area for current flow (reducing IR drop) while maintaining compact horizontal footprint for high pixel density.
Solution Approach 2:
The wiring path is segmented into multiple shorter segments across different conductive layers, connected by via holes. This segmentation reduces the length of high-current paths in each layer, lowering IR drop, while the stacked arrangement maintains compact overall area for high pixel density.
4Reliability
If signal lines are separated to reduce interference, then the short circuit probability decreases, but the wiring complexity increases
Solution Approach 1:
The patent uses vertical stacking of conductive layers to separate signal lines that would otherwise be crowded in the horizontal plane. This three-dimensional arrangement naturally isolates adjacent wiring paths, reducing interference and short circuit probability while the regular stacked pattern keeps the fabrication process relatively systematic.
Data Source
AI summary
The present disclosure provides an array substrate and a display device. The array substrate includes a base substrate and a scan line, a data line, a power supply line, a sensing line, a pixel driving circuit and a light-emitting unit that are sequentially stacked on the base substrate. The array substrate also includes a gate layer, a first conductive layer, a second conductive layer, and a third conductive layer. The first electrode of the storage capacitor is at least disposed at the first conductive layer, and the second electrode of the storage capacitor is at least disposed at the second conductive layer. The data line, the power supply line, and the sensing line are disposed at the third conductive layer.