OLED Array Substrate Capacitance Ratio for Dark State Margin
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Solution Overview
Problem
Existing OLED display technologies face challenges in maintaining a constant driving current to control illumination, leading to inefficiencies in pixel driving circuits.
Innovation Solution
The array substrate incorporates a pixel driving circuit with a driving transistor, data write transistor, compensating transistor, storage capacitor, and specific capacitance configurations to manage gate scanning signals and voltage supply lines, optimizing the ratio of first capacitance to second capacitance for improved dark state margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional pixel driving circuit is used in OLED display, then the circuit can drive the light emitting element, but the driving current cannot be kept constant leading to poor display uniformity
Solution Approach 1:
The patent introduces a dual-semiconductor-layer structure where the first semiconductor material layer contains active layers of driving and data write transistors, and the second semiconductor material layer contains the active layer of compensating transistor. This structural parameter change enables separate control of transistor characteristics to maintain constant driving current
Solution Approach 2:
The pixel driving circuit is segmented into multiple functional components with dedicated capacitances: first capacitance between gate connecting pad and second semiconductor material layer/first node connecting line, and second capacitance between first node connecting line and second gate line. The ratio of first capacitance to second capacitance is controlled between 1.5 to 4.0 to optimize performance
2Reliability
If the driving current is not kept constant, then the pixel driving circuit can operate with simpler design, but false contouring and image retention occur
Solution Approach 1:
The patent specifically controls the ratio of first capacitance to second capacitance between 1.5 to 4.0, and positions the gate connecting pad in a layer different from the first gate line. These parameter changes enhance the dark state margin by optimizing charge storage and distribution in the pixel driving circuit
Solution Approach 2:
The first node connecting line serves as an intermediary element that connects the gate electrode of the driving transistor with the first electrode of the compensating transistor, and is involved in forming both the first capacitance and second capacitance. This intermediary structure enables precise control of voltage distribution to prevent false contouring and image retention
Data Source
AI summary
An array substrate is provided. The array substrate includes a first semiconductor material layer and a second semiconductor material layer on a side of the first semiconductor material layer away from a base substrate. The first semiconductor material layer includes at least active layers of the driving transistor and the data write transistor. The second semiconductor material layer includes at least an active layer of the compensating transistor. A first capacitance is at least partially formed between a gate connecting pad and at least one of the second semiconductor material layer or a first node connecting line. A second capacitance is formed between the first node connecting line and a respective second gate line. The first capacitance is greater than the second capacitance.