OLED Array Substrate Corner Wiring Layout

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Solution Overview

Problem

In OLED display technology, the wirings of the multiplexing circuit at the corner area and other circuits are prone to interference, affecting each other's functionality, which complicates the design and increases the size and cost of the array substrate.

Innovation Solution

The array substrate design includes a base substrate with a display area and peripheral areas, featuring groups of connecting lines that route gate, light emitting control, and power signals between the display area and the corner area, where multiplexing circuits are positioned. These connecting lines are carefully layered to avoid overlap with multiplexing units, reducing interference and allowing for a more compact and cost-effective layout.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the multiplexing circuit is positioned in the corner area to reduce the size of the array substrate, then the area of the array substrate is reduced, but the wiring of the multiplexing circuit becomes prone to interference with other circuits

Engineering Contradiction:
Improvearea of array substrateVSAvoidinterference between circuits
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies dimensional separation by routing connecting lines through different layers (first through fourth signal line layers) to connect the multiplexing circuit in the corner area to the display area. This vertical dimensionality allows wiring to pass through spaces between adjacent multiplexing units without overlapping, resolving the interference problem while maintaining the compact corner-area layout.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the wiring path into multiple independent connecting lines (first, second, third, and fourth connecting lines) that route through different signal line layers. Each connecting line is independently positioned to pass between specific multiplexing units, dividing the complex wiring problem into manageable segments that avoid interference with other circuits.

Inventive Principle:
Principle #1Segmentation

2Reliability

If connecting lines are routed through multiple layers to avoid overlap with multiplexing units, then interference is reduced, but the device complexity increases

Engineering Contradiction:
Improveinterference between circuitsVSAvoidcomplexity of wiring layout
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses a standardized multi-layer signal line structure where each layer serves multiple functions: signal transmission and spatial separation. The same layering approach is applied to all connecting lines (first through fourth connecting lines), creating a universal wiring pattern that reduces design complexity despite the multi-layer implementation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs a flexible layering strategy where the specific layer assignment of connecting lines can be dynamically adjusted based on the required routing path. For example, the first connecting line may use the first or second signal line layer depending on which path provides better separation from multiplexing units, allowing adaptive optimization without increasing fundamental complexity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentEP4148797B1Array substrate and display device
Publication Date: 2024.06.12 BOE TECHNOLOGY GROUP CO LTD
  • EP4148797B1 patent drawingFigure 1A~1B
  • EP4148797B1 patent drawingFigure 2A
  • EP4148797B1 patent drawingFigure 2B

AI summary

Provided are an array substrate and a display device. The array substrate includes: a base substrate including a display area and a peripheral area including a first peripheral area located on one side of the display area and a corner area adjacent to the first peripheral area; a plurality of sub-pixels, data lines, gate lines and light emitting control lines located at the display area; a plurality of groups of connecting lines located at least at the corner area, each group of which including a plurality of connecting lines including a gate connecting line electrically connected to a gate line and a light emitting control connecting line electrically connected to a light emitting control line; a gate driving circuit; a light emitting control driving circuit located on one side of the gate driving circuit away from the display area; a plurality of data signal input lines; and a multiplexing circuit. The orthographic projection of each connecting line on the base substrate passes between the orthographic projections of two adjacent multiplexing units on the base substrate and does not overlap with the orthographic projections of the multiplexing units on the base substrate.