OLED Array Substrate Reset Thin Film Transistor Via Structure
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Solution Overview
Problem
In OLED display devices, the shift of threshold voltage in driving thin film transistors due to manufacturing defects or aging components leads to non-uniform current distribution across pixels, resulting in uneven brightness.
Innovation Solution
An array substrate design featuring a reset unit with a shared reset signal line between adjacent rows of pixel units, where the reset signal line, gate electrode, and source/drain electrodes are connected through a single via, allowing for a simplified manufacturing process and reduced aperture ratio, enabling higher-resolution displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset unit is added to each pixel unit to compensate for threshold voltage shift, then display uniformity is improved, but aperture ratio decreases and manufacturing complexity increases
Solution Approach 1:
The patent merges the reset signal line with the gate electrode and source/drain electrodes by connecting them through a single via structure. This integration allows the reset unit to share conductive paths with other pixel components, reducing the total area occupied by the reset unit while maintaining its compensatory function for threshold voltage shift.
Solution Approach 2:
The via structure serves multiple functions simultaneously: it connects the reset signal line to the gate electrode, connects to the source/drain electrodes, and acts as a shared conductive path. This multi-functionality reduces the need for separate dedicated connection structures, thereby minimizing the area occupied by the reset unit.
2Reliability
If a reset unit is added to each pixel unit to compensate for threshold voltage shift, then display uniformity is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple connection functions into a single via structure that simultaneously connects the reset signal line, gate electrode, and source/drain electrodes. This merging reduces the number of separate manufacturing steps and alignment processes required, thereby reducing manufacturing complexity while maintaining the reset unit's functionality.
Solution Approach 2:
The via structure is designed to perform multiple connection functions within a single structural element. By making the via universal for connecting different components (reset signal line, gate electrode, source/drain electrodes), the patent reduces the overall device complexity and simplifies the manufacturing process compared to having separate dedicated connection structures for each component.
3Reliability
If multiple separate vias are used to connect reset signal line, gate electrode, and source/drain electrodes, then connection reliability is improved, but manufacturing complexity and aperture ratio loss increase
Solution Approach 1:
The patent merges multiple separate via connections into a single integrated via structure that simultaneously establishes electrical connections between the reset signal line, gate electrode, and source/drain electrodes. This consolidation maintains connection reliability by ensuring all necessary connections are made through a single robust structural element, while reducing manufacturing complexity by eliminating multiple alignment and formation steps.
Data Source
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AI summary
The present application discloses an array substrate comprising a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line. Every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group, each pixel unit group comprises a plurality of columns of pixel units. Each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer on the base substrate, a first insulating layer on a side of the conductive semiconductor layer distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer, a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode. The metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode. The metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group through two corresponding drain vias. The source electrode is electrically connected to the first semiconductor electrode through the source via.