Electroluminescence Display Asymmetric Transistor Arrays
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Solution Overview
Problem
In electroluminescence displays, process deviations during the formation of transistor arrays can lead to shifts in specific layers, resulting in changes in electrical characteristics such as parasitic capacitance, causing brightness deviations between subpixels and poor picture quality.
Innovation Solution
The electroluminescence display is designed with transistor arrays arranged in intersecting directions, where OLEDs of different colors are connected to specific types of transistor arrays (A and B types) to minimize brightness deviations, and power source lines are shared between adjacent transistor arrays to reduce the number of high potential power source lines, thereby maintaining consistent electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If process deviation occurs during transistor array formation, then layer shifts occur, but electrical characteristics such as parasitic capacitance change causing brightness deviation
Solution Approach 1:
The patent introduces asymmetry by creating two different types of transistor arrays (A-type and B-type) with different layouts. This asymmetric design allows the system to compensate for process deviations - when layer shifts occur, one type of transistor array experiences less electrical characteristic variation than the other, enabling selection of the more reliable type for each pixel to maintain brightness consistency
Solution Approach 2:
The patent changes the layout parameters of transistor arrays to create two distinct configurations. By varying the arrangement of transistors and capacitors within the array, the electrical characteristics (particularly parasitic capacitance) respond differently to the same process deviation, allowing compensation for manufacturing imprecision
2Reliability
If separate power source lines are used for each transistor array, then electrical characteristics can be independently controlled, but the number of power source lines increases
Solution Approach 1:
The patent merges power source lines by having adjacent transistor arrays of the same type share common power source lines. Instead of providing separate power lines to each transistor array, the design combines power delivery paths, reducing the total number of power source lines while maintaining electrical characteristic control through the symmetric placement of arrays relative to shared lines
3Ease of manufacture
If transistor arrays are arranged symmetrically, then layout simplicity is improved, but brightness deviation occurs due to parasitic capacitance changes
Solution Approach 1:
The patent deliberately introduces asymmetry by defining two different transistor array types (A-type and B-type) with different internal layouts. This asymmetric approach replaces simple symmetric repetition with a more complex but effective scheme where different array types compensate for each other's sensitivity to process deviations, improving brightness consistency
Solution Approach 2:
The patent applies local quality by assigning different transistor array configurations to different locations or groups of pixels. Instead of using a uniform layout throughout, the design varies the array type locally to compensate for position-dependent process variations and maintain consistent electrical characteristics across the display
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces brightness deviations between subpixels, enhancing picture quality by ensuring consistent driving currents and minimizing color distortion, thus improving display resolution and lifespan.
Implementation Method 1
The OLEDs are electrically connected to the transistor arrays, and emit lights of first, second and third colors
Data Source
AI summary
An electroluminescence display comprises transistor arrays, OLEDs, and power source lines. The transistor arrays are arranged in a first direction and a second direction intersecting the first direction. The OLEDs are electrically connected to the transistor arrays, and emit first, second and third colors. The power source lines apply power source voltage to the transistor arrays. The transistor arrays are disposed adjacently in the first direction to share one power source line positioned between the transistor arrays, and include a transistor array of an A type and a transistor array of a B type symmetrical to each other with respect to a reference line extended in the second direction. All the OLEDs emitting a light of any one of the first to third colors are connected to the transistor array of the A type. All the OLEDs emitting another of the first to third colors are connected to the transistor array of the B type.