OLED Display Blocking Layer Layout for Kickback Voltage Suppression
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Solution Overview
Problem
High-resolution organic light emitting diode (OLED) displays face challenges in minimizing parasitic capacitance and residual images due to the kickback voltage from transistors, affecting display quality and resolution.
Innovation Solution
Incorporating a blocking layer that overlaps the driving transistor and is connected to the driving voltage line, which prevents potential changes and minimizes parasitic capacitance by receiving a constant driving voltage, thereby improving display quality and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-resolution OLED display is implemented with integrated transistors, then display resolution is improved, but parasitic capacitance and residual images increase due to kickback voltage from transistors
Solution Approach 1:
A blocking layer is introduced as an intermediary component between the substrate and the second transistor. This blocking layer acts as a mediator to prevent kickback voltage from the second transistor from affecting the first transistor, thereby reducing parasitic capacitance and residual images while maintaining high display resolution
Solution Approach 2:
The transistor structure is segmented into multiple layers with distinct functions. The first transistor handles driving signals while the second transistor controls emission, separated by the blocking layer. This segmentation allows independent optimization of each transistor's function and prevents interference between them, resolving the contradiction between integration and parasitic effects
Data Source
AI summary
An organic light emitting diode display according to an exemplary embodiment includes: a substrate; a first buffer layer on the substrate; a first semiconductor layer on the first buffer layer; a first gate insulating layer on the first semiconductor layer; a first gate electrode and a blocking layer on the first gate insulating layer; a second buffer layer on the first gate electrode; a second semiconductor layer on the second buffer layer; a second gate insulating layer on the second semiconductor layer; and a second gate electrode on the second gate insulating layer.