OLED Display Load Capacitance Equalization via Parasitic Overlap
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In OLED display devices, the difference in load capacitance between various regions due to varying numbers of light emitting structures and gate wirings leads to luminance differences, reducing visibility.
Innovation Solution
The OLED display device incorporates a stack structure in the peripheral region with a parasitic capacitor, where the active pattern and upper gate wiring overlap, equalizing the load capacitance across different regions by adjusting the overlap areas and distances of active and gate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of light emitting structures and gate wirings varies across different regions, then the device can accommodate different functional requirements, but load capacitance differences cause luminance non-uniformity
Solution Approach 1:
The patent applies local quality by configuring different numbers of light emitting structures and gate wirings in different regions (first region has more structures, second region has fewer structures) to meet specific functional requirements, while simultaneously introducing parasitic capacitors in the first region to locally compensate for capacitance differences and maintain luminance uniformity across the display
2Productivity
If more gate wirings are added to certain regions to support more light emitting structures, then the region can drive more pixels, but the load capacitance increases causing luminance differences
Solution Approach 1:
The patent uses parasitic capacitors as counterweight elements in the first region, where the capacitance of these parasitic capacitors is designed to compensate for the excess load capacitance caused by the higher number of gate wirings and light emitting structures, thereby balancing the total load capacitance across regions and eliminating luminance non-uniformity
3Reliability
If the overlap area between active pattern and gate wiring is increased, then parasitic capacitance increases to compensate for load capacitance differences, but the device complexity increases
Solution Approach 1:
The patent merges the parasitic capacitor formation with the existing gate wiring structure by making the gate wiring overlap with the active pattern, thereby generating parasitic capacitance as a byproduct of the wiring layout rather than as a separate component, which reduces device complexity while achieving luminance uniformity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes luminance differences between regions, enhancing the visibility of the OLED display device by equalizing load capacitance and reducing the impact of static electricity on semiconductor elements.
Implementation Method 1
a stack structure in the peripheral region with a parasitic capacitor, where the active pattern and upper gate wiring overlap, equalizing the load capacitance across different regions
Data Source
AI summary
An organic light emitting diode (“OLED”) display device includes a substrate having a display region having a light emitting region and a peripheral region surrounding the light emitting region, a pad region at a first side of the display region, and a trench at a second side of the display region, a plurality of light emitting structures on the light emitting region of the substrate, an active pattern along a profile of the trench on the peripheral region of the substrate, the active pattern being adjacent to the trench and including a pattern protrusion, and an upper gate wiring on and overlapping the active pattern, the upper gate wiring having a wiring protrusion adjacent to the pattern protrusion.