OLED Array Substrate Capacitor Area Expansion

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Solution Overview

Problem

Existing OLED array structures are limited by the gate area of the thin film transistor, restricting the capacitor area and thus the electrical performance, particularly in achieving higher pixel density and storage capacity.

Innovation Solution

A manufacturing method for an organic light-emitting diode array substrate where two metal pattern layers are used as the capacitor electrode plates, deposited over the gate of the driving transistor, allowing for a larger capacitor area independent of the gate area, thereby enhancing storage capacity and response rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the gate of the thin film transistor serves as the bottom electrode plate of the capacitor, then the structure is simplified, but the capacitor area is limited by the gate area

Engineering Contradiction:
ImprovestructureVSAvoidcapacitor area
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent extends the capacitor electrode plates in the vertical dimension by forming them as multi-layer structures stacked above the gate, rather than being confined to the gate plane. This allows the capacitor area to exceed the gate area by utilizing the third dimension (height), effectively decoupling capacitor size from gate size while maintaining electrical connection through via holes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If the capacitor area is increased to improve storage capacity, then the electrical performance is improved, but the pixel area increases reducing pixel density

Engineering Contradiction:
Improvestorage capacityVSAvoidpixel area
Core Design Contradiction:
Quantity of substanceVSArea of moving object

Solution Approach 1:

By stacking capacitor electrode plates vertically above the gate region, the patent increases storage capacity without expanding the horizontal pixel footprint. The capacitor electrodes extend in the vertical dimension (Z-axis) rather than requiring additional horizontal space, allowing high pixel density to be maintained while achieving larger effective capacitor area through multi-layer stacking.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent nests the capacitor structure within the existing transistor structure by placing capacitor electrode plates above and around the gate region. The capacitor shares the same horizontal footprint as the transistor, with electrode plates stacked in layers above the gate, effectively nesting the capacitor function within the transistor's spatial envelope to avoid increasing overall pixel area.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Quantity of substance

If the distance between electrode plates is reduced to increase capacitance, then the capacitance value increases, but the dielectric layer thickness decreases increasing breakdown risk

Engineering Contradiction:
Improvecapacitance valueVSAvoidbreakdown risk
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent employs composite dielectric structures with multiple dielectric layers having different materials and properties. By stacking different dielectric materials with varying permittivity values and breakdown strengths, the system achieves high capacitance through material composition rather than simply reducing physical distance, thereby maintaining reliability while increasing capacitance value.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS11251253B2Organic light-emitting diode array substrate and manufacturing method thereof
Publication Date: 2022.02.15 WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO LTD
  • US11251253B2 patent drawing
  • US11251253B2 patent drawing
  • US11251253B2 patent drawing

AI summary

An organic light-emitting diode array substrate and manufacturing method thereof are provided. The manufacturing method includes forming a semiconductor layer, a gate insulating layer, a gate, and a first insulating layer on a substrate; forming a first metal pattern on the first insulating layer, and the first metal pattern connecting to the gate through the through hole; forming a second insulating layer covering the first metal pattern on the first insulating layer; and forming a second metal pattern on the second insulating layer so that the second metal pattern and the first metal pattern overlap each other to form a capacitor.