OLED Storage Capacitor Shielding for Stable Gray Levels
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Solution Overview
Problem
In OLED displays, parasitic capacitance between data lines and capacitor plates leads to voltage changes affecting the gate of the driving TFT, causing abnormalities in gray level and image display.
Innovation Solution
The OLED display substrate includes a base substrate with a driving thin film transistor and an energy storage capacitor, where the second capacitor plate is electrically connected to the gate of the driving TFT, and a first shielding portion is disposed between the second capacitor plate and the first data line to reduce capacitive coupling and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the data line and capacitor plate are disposed close to each other on the OLED display substrate, then the device area is reduced and integration is improved, but parasitic capacitance between the data line and capacitor plate increases, causing voltage changes and gray level abnormalities
Solution Approach 1:
A shielding portion is introduced as an intermediary element disposed between the data line and the capacitor plate. This shielding portion acts as a mediator that blocks the capacitive coupling between the two conductive elements, reducing the parasitic capacitance effect while allowing both elements to remain in close proximity for compact design
Solution Approach 2:
The harmful parasitic capacitance effect is extracted and isolated by introducing a separate shielding portion. The shielding portion is electrically connected to a reference potential (such as ground or power supply voltage), thereby removing the unwanted capacitive coupling from the signal path between the data line and capacitor plate
2Device complexity
If the capacitor plate is integrated with the gate of the driving TFT to save space, then the device complexity is reduced, but the parasite capacitance between the data line and the integrated capacitor plate causes voltage changes on the gate, leading to image abnormalities
Solution Approach 1:
The shielding portion serves as a protective intermediary between the integrated gate-capacitor structure and the data line. By being electrically connected to a stable reference potential, the shielding portion isolates the gate voltage from unwanted capacitive fluctuations caused by data line voltage changes, thereby maintaining image quality stability while preserving the integrated design
3Ease of manufacture
If the first capacitor plate is disposed on the side of the second capacitor plate away from the base substrate, then the manufacturing process is simplified, but the parasitic capacitance between the data line and second capacitor plate still causes voltage changes on the gate
Solution Approach 1:
The shielding portion is strategically disposed between the data line and the second capacitor plate to block the capacitive coupling path. This intermediary structure reduces the parasitic capacitance effect without interfering with the stacked capacitor plate configuration, maintaining both ease of manufacture and electrical performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively shields capacitive coupling, reducing parasitic capacitance and minimizing voltage changes on the gate of the driving TFT, thereby improving the stability of gray level and image quality.
Implementation Method 1
Parasite capacitance is formed between the data line and the capacitor plate integrated with the gate of the driving TFT
Implementation Method 2
a first shielding portion which is disposed at least partially between the second capacitor plate and the first data line
Data Source
AI summary
An organic light emitting diode display substrate, comprises: a base substrate, and a first data line, a driving thin film transistor and an energy storage capacitor, wherein the energy storage capacitor comprises a first capacitor plate and a second capacitor plate disposed opposite to each other, and the second capacitor plate is electrically connected to a gate of the driving thin film transistor, in a direction away from the base substrate, the first capacitor plate is disposed between the first data line and the second capacitor plate. The display substrate further comprises a shielding portion. The shielding portion is between the second capacitor plate and the first data line in a direction perpendicular to the base substrate, and an orthographic projection of the shielding portion on the base substrate at least partially overlap an orthographic projection of the first data line on the base substrate.