OLED Panel Capacitor Layout for Higher Luminance and Resolution
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Solution Overview
Problem
Existing organic light emitting display devices face challenges in achieving high luminance and resolution while maintaining a sufficient light emitting area, as they require efficient space arrangement and connection structures between elements, and current processes are complex and require multiple masks.
Innovation Solution
The organic light emitting display panel design includes a substrate with a conductive layer, buffer layer, active layer, insulating films, and conductive layers with overlapping contact holes to reduce the non-light emitting area and increase the storage capacitor capacity without reducing the light emitting area, allowing for high luminance and resolution, and simplifies the manufacturing process by forming contact holes in the buffer layer and insulating film through the same process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If the area of non-light emitting region is reduced to increase light emitting area, then luminance is improved, but the storage capacitor area is reduced
Solution Approach 1:
The patent merges the storage capacitor with the transistor structure by positioning the capacitor within the transistor's active region. The capacitor utilizes the gate electrode and gate insulating film of the transistor, combining two functional elements into a compact integrated structure that reduces overall pixel area while maintaining both light emitting and storage functions
Solution Approach 2:
The patent employs multi-layer stacking to create three-dimensional space utilization. Contact holes from different layers are positioned to overlap vertically, allowing conductive patterns to connect through multiple levels. This vertical arrangement reduces the horizontal footprint of the pixel, enabling larger light emitting areas while preserving capacitor functionality in the vertical dimension
2Manufacturing precision
If multiple masks are used to form buffer layer and first insulating film separately, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the formation of the buffer layer and first insulating film into a single deposition process step. By depositing both layers simultaneously or in sequence without intermediate masking operations, the process reduces the total number of masks required while maintaining the structural integrity and functional separation of the two insulating layers
Solution Approach 2:
The buffer layer and first insulating film serve multiple functions: electrical insulation, mechanical protection, and process integration. By designing these layers to be formed together, the patent creates a multi-functional composite structure that simplifies the manufacturing process while maintaining the necessary electrical isolation and structural support functions
3Ease of manufacture
If contact holes are formed in buffer layer and first insulating film through same process, then ease of manufacture is improved, but manufacturing precision may deteriorate
Solution Approach 1:
The patent segments the contact hole formation process into distinct stages corresponding to different insulating layers. Contact holes are formed sequentially through the buffer layer and then through the first insulating film, with each stage optimized for its specific layer thickness and material properties. This segmented approach maintains precision while simplifying overall manufacturing
Solution Approach 2:
The patent utilizes vertical stacking and overlapping of contact holes from different layers to achieve precise alignment. By positioning contact holes in the buffer layer and first insulating film to overlap in the vertical dimension, the patent reduces the horizontal alignment tolerance requirements while maintaining electrical connection precision through the multi-layer structure
Data Source
AI summary
A display panel of an organic light emitting display device includes a buffer layer disposed on a first conductive layer, and including a first contact hole, an active layer disposed on the buffer layer, and including an active pattern and a conductive pattern disposed on the active pattern, a first insulating film disposed on or over the active layer and the buffer layer, and including a second contact hole overlapping with the first contact hole, a second conductive layer disposed on the first insulating film, and contacting the first conductive layer through the first contact hole and the second contact hole, a plate disposed in the same layer as the second conductive layer, and spaced apart from the second conductive layer, and each of the first conductive layer, the active layer, and the plate serves as an electrode of a storage capacitor, thereby implementing a high-capacity storage capacitor for the display panel.