OLED Capacitor Layout Design for Storage Capacitance and Aperture Ratio

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Solution Overview

Problem

Active matrix organic light emitting diode (AMOLED) displays require high storage capacitance and high aperture ratio, which existing capacitor layout designs fail to adequately satisfy.

Innovation Solution

A capacitor layout design for an OLED display panel is improved by dividing the sub-pixel area into distinct regions for driving TFT, capacitor, and switching TFT, with specific patterned semiconductor and conductive layers to enhance storage capacitance and aperture ratio, including the formation of additional capacitors and optimized conductive layer configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional capacitor layout design is used in AMOLED display, then the display can be manufactured with standard processes, but the storage capacitance is insufficient and aperture ratio is reduced

Engineering Contradiction:
Improvestorage capacitanceVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The pixel structure is segmented into distinct functional regions: a first region containing the driving TFT, a second region containing the storage capacitor, and a third region containing the switching TFT. This segmentation allows each component to be optimized independently, enabling the capacitor to achieve high storage capacitance through dedicated layout design while maintaining overall pixel efficiency and aperture ratio.

Inventive Principle:
Principle #1Segmentation

2Reliability

If capacitor size is increased to improve storage capacitance, then storage capacitance increases, but the aperture ratio of the display decreases

Engineering Contradiction:
Improvestorage capacitanceVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The capacitor structure utilizes vertical stacking in the third dimension by forming the capacitor electrode, insulating layer, and conductive layer in multiple stacked layers. This three-dimensional capacitor layout increases the effective capacitance area without expanding the planar footprint, thereby maintaining high aperture ratio while achieving high storage capacitance through vertical space utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If more components are added to increase storage capacitance, then storage capacitance improves, but device complexity increases

Engineering Contradiction:
Improvestorage capacitanceVSAvoidcapacitor layout complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The conductive layer is designed to serve multiple functions: it acts as the upper electrode for the storage capacitor, provides electrical connection to the pixel circuit, and can be integrated with other pixel structures. This multi-functional design achieves high storage capacitance without adding separate dedicated capacitor components, thereby reducing overall device complexity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8158986B2System for display images and fabrication method thereof
Publication Date: 2012.04.17 RED OAK INNOVATIONS LTD
  • US8158986B2 patent drawing
  • US8158986B2 patent drawing
  • US8158986B2 patent drawing

AI summary

A system for displaying images including a display panel and a fabrication method thereof are provided. The display panel includes a substrate having a first, second and third areas, a first patterned semiconductor layer disposed over the first area of the substrate, a first insulating layer covering the first patterned semiconductor layer and the first, the second and the third areas of the substrate, a second patterned semiconductor layer disposed on the first insulating layer of the first and the third areas respectively, a second insulating layer covering the second patterned semiconductor layer and the first insulating layer, and a patterned conductive layer disposed on the second insulating layer to form a first thin-film transistor at the first area and a second thin-film transistor at the third area.